Foto von Daniel Müller-Gritschneder

Dr.-Ing. Daniel Müller-Gritschneder

Technische Universität München

Lehrstuhl für Entwurfsautomatisierung (Prof. Schlichtmann)

Postadresse

Postal:
Arcisstr. 21
80333 München

Publications

Daniel Mueller-Gritschneder, Martin Dittrich, Marc Greim, Keerthikumara Devarajegowda, Wolfgang Ecker, Ulf Schlichtmann
The Extendable Translating Instruction Set Simulator (ETISS) interlinked with an MDA Framework for fast RISC Prototyping
In: IEEE International Symposium on Rapid System Prototyping (RSP)
October 2017

Daniel Mueller-Gritschneder, Andreas Gerstlauer
Host-Compiled Simulation
In: Handbook of Hardware/Software Codesign
Springer Netherlands, June 2017

Yong Hu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
A Model-based Framework For Networks-on-Chip Design Space Exploration
2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISTECS)
January 2017

Daniel Mueller-Gritschneder, Marc Greim, Ulf Schlichtmann
Safety Evaluation based on Virtual Prototypes: Fault Injection with Multi-level Processor Models
In: International Symposium on Integrated Circuits (ISIC)
December 2016

Petra R. Maier, Veit B. Kleeberger, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Fault Injection at Host-Compiled Level with Static Fault Set Reduction for SoC Firmware Robustness Testing
In: International conference on Hardware/Software codesign and system synthesis (CODES+ISSS)
October 2016

Munish Jassi, Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Hardware-Accelerated Software Libraries Drivers Generation for IP-Centric SoC Designs
In: Great Lakes Symposium on VLSI (GLS-VLSI)
May 2016

Petra R. Maier, Veit B. Kleeberger, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Fehlerinjektion auf Unit-Ebene zur Robustheitsverifikation eingebetteter Software
In: edaWorkshop
May 2016

Munish Jassi, Yong Hu, Jian Lyu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
GRIP: Graph-Rewriting-Based IP-Integration - An EDA Tool for Software Defined SoC Design
In: Design, Automation and Test in Europe (DATE) University Booth
March 2016

Petra R. Maier, Daniel Mueller-Gritschneder, Ulf Schlichtmann, Veit B. Kleeberger
Embedded Software Reliability Testing by Unit-Level Fault Injection
In: IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC)
January 2016

Munish Jassi, Benjamin Bordes, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Automation of FPGA Performance Monitoring and Debugging Using IP-XACT and Graph-Grammars
In: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
September 2015

Michael Glaß, Hananeh Aliee, Liang Chen, Mojtaba Ebrahimi, Faramarz Khosravi, Veit B. Kleeberger, Alexandra Listl, Daniel Mueller-Gritschneder, Fabian Oboril, Ulf Schlichtmann, Mehdi B. Tahoori, Jürgen Teich, Norbert Wehn, Christian Weis
Application-aware cross-layer reliability analysis and optimization
it – Information Technology 2015 57, 159–169
June 2015

Munish Jassi, Daniel Mueller-Gritschneder, Ulf Schlichtmann
GRIP: Grammar-Based IP Integration and Packaging for Acceleration-Rich SoC Designs
In: ACM/IEEE Design Automation Conference (DAC)
June 2015

Marc Greim, Daniel Mueller-Gritschneder, Ulf Schlichtmann
C++ Processor Models for Accelerated Multi-level Error Effect Simulation
In: edaWorkshop
May 2015

Oliver Bringmann, Wolfgang Ecker, Andreas Gerstlauer, Ajay Goyal, Daniel Mueller-Gritschneder, Prasanth Sasidharan, Simranjit Singh
The Next Generation of Virtual Prototyping: Ultra-fast Yet Accurate Simulation of HW/SW Systems
In: Design, Automation and Test in Europe (DATE)
March 2015

Daniel Mueller-Gritschneder
VHDL Code Generation from IP-Xact using the Eclipse Modeling Framework (EMF)
In: Design and Verification Conference and Exhibition (DVCon) Tutorials
March 2015

Yong Hu, Daniel Mueller-Gritschneder, Sepulveda, M.J., Gogniat, G., Ulf Schlichtmann
Automatic ILP-based Firewall Insertion for Secure Application-Specific Networks-on-Chip
In: Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC), 2015 Ninth International Workshop on
January 2015

Daniel Mueller-Gritschneder, Petra R. Maier, Marc Greim, Ulf Schlichtmann
SystemC-based Multi-level Error Injection for the Evaluation of Fault-tolerant Systems
In: International Symposium on Integrated Circuits (ISIC)
December 2014

Dip Goswami, Daniel Mueller-Gritschneder, Basten Twan, Ulf Schlichtmann, Samarjit Chakraborty
Fault-tolerant Embedded Control Systems for Unreliable Hardware
In: International Symposium on Integrated Circuits (ISIC)
December 2014

Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann
Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 33(10), 1503-1516
October 2014

Andreas Herkersdorf, Hananeh Aliee, Michael Engel, Michael Glaß, Christina Gimmler-Dumont, Jörg Henkel, Veit B. Kleeberger, Michael A. Kochte, Johannes M. Kühn, Daniel Mueller-Gritschneder, Sani R. Nassif, Holm Rauchfuss, Wolfgang Rosenstiel, Ulf Schlichtmann, Muhammad Shafique, Mehdi B. Tahoori, Jürgen Teich, Norbert Wehn, Christian Weis, Hans-Joachim Wunderlich
Resilience Articulation Point (RAP): Cross-layer Dependability Modeling for Nanometer System-on-chip Resilience
Microelectronics Reliability 54(6-7), 1066-1074
June 2014

J. H. Oetjens, N. Bannow, M. Becker, Oliver Bringmann, A. Burger, Moomen Chaari, Samarjit Chakraborty, Rolf Drechsler, Wolfgang Ecker, K. Gr\, Th. Kruse, C. Kuznik, H. M. Le, A. Mauderer, W. M\, Daniel Mueller-Gritschneder, F. Poppen, H. Post, S. Reiter, Wolfgang Rosenstiel, S. Roth, Ulf Schlichtmann, A. von Schwerin, B. A. Tabacaru, Alexander Viehl
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges
In: Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference
June 2014

Felix Miller, Vladimir Todorov, Thomas Wild, Daniel Mueller-Gritschneder, Andreas Herkersdorf, Ulf Schlichtmann
A TSV-Property-aware Synthesis Method for Application-Specific 3D-NoCs Design
In: Design Automation and Test in Europe (DATE), Friday Workshop on 3D Integration
March 2014

Veit B. Kleeberger, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Technology-Aware System Failure Analysis in the Presence of Soft Errors by Mixture Importance Sampling
In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
October 2013

Veit B. Kleeberger, Christina Gimmler-Dumont, Christian Weis, Andreas Herkersdorf, Daniel Mueller-Gritschneder, Sani R. Nassif, Ulf Schlichtmann, Norbert Wehn
A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience
IEEE Micro 33(4)
July 2013

Amit Verma, Pritpal Multani, Daniel Mueller-Gritschneder, Vladimir Todorov, Ulf Schlichtmann
A Greedy Approach for Latency-bounded Deadlock-free Routing Path Allocation for Application-specific NoCs
In: International Symposium on Networks-on-Chip (NOCS)
April 2013

Carsten Uphoff, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Application of Dempster-Shafer Theory to Task Mapping under Epistemic Uncertainty
2013 IEEE International Systems Conference
April 2013

Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Fast Cache Simulation for Host-Compiled Simulation of Embedded Software
In: Design, Automation and Test in Europe (DATE)
March 2013

Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Analytical Timing Estimation for Temporally Decoupled TLMs Considering Resource Conflicts
In: Design, Automation and Test in Europe (DATE)
March 2013

Daniel Mueller-Gritschneder, Kun Lu, Erik Wallander, Marc Greim, Ulf Schlichtmann
A Virtual Prototyping Platform for Real-time Systems with a Case Study for a Two-wheeled Robot
In: Design, Automation and Test in Europe (DATE)
March 2013

Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann
A Spectral Clustering Approach to Application-Specific Network-on-Chip Synthesis
In: Design, Automation and Test in Europe (DATE)
March 2013

Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Memory Access Reconstruction Based on Memory Allocation Mechanism for Source-Level Simulation of Embedded Software
In: IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC)
January 2013

Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Hierarchical Control Flow Matching for Source-level Simulation of Embedded Software
In: IEEE International Symposium on System-on-Chip
October 2012

Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Accurately Timed Transaction Level Models for Virtual Prototyping at High Abstraction Level
In: Design, Automation and Test in Europe (DATE)
March 2012

Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann
Automated Construction of a Cycle-Approximate Transaction Level Model of a Memory Controller
In: Design, Automation and Test in Europe (DATE)
March 2012

Daniel Mueller-Gritschneder, Kun Lu, Ulf Schlichtmann
Control-flow-driven Source Level Timing Annotation for Embedded Software Models on Transaction Level
In: EUROMICRO Conference on Digital System Design (DSD)
September 2011

Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Removal of Unnecessary Context Switches from the SystemC Simulation Kernel for Fast VP Simulation
In: International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)
July 2011

Kun Lu, Daniel Mueller-Gritschneder, Wolfgang Ecker, Volkan Esen, Michael Velten, Ulf Schlichtmann
An Approach toward Accurately Timed TLM+ for Embedded System Models
In: edaWorkshop
May 2011

Dominik Lorenz, Martin Barke, Daniel Mueller-Gritschneder, Georg Georgakos, Ulf Schlichtmann
Aging model for timing analysis at register-transfer-level
In: ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems
March 2010

Daniel Mueller-Gritschneder, Helmut Graeb
Computation of Yield-optimized Pareto Fronts for Analog Integrated Circuit Specifications
In: Design, Automation and Test in Europe (DATE)
March 2010

Daniel Mueller-Gritschneder, Helmut Graeb
Berechnung von ausbeuteoptimierten Spezifikationsparetofronten für analoge integrierte Schaltungen
In: ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG)
March 2010

Daniel Mueller-Gritschneder, Helmut Graeb, Ulf Schlichtmann
A Successive Approach to Compute the Bounded Pareto Front of Practical Multi-objective Optimization Problems
SIAM Journal on optimization 20(2), 915--934
July 2009

Daniel Mueller-Gritschneder
Deterministic Performance Space Exploration of Analog Integrated Circuits Considering Process Variations and Operating Conditions
PhD Thesis
Technische Universität München
June 2009

Helmut Graeb, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Pareto Optimization of Analog Circuits considering Variability
International Journal of Circuit Theory and Applications 37(2), 283-299
March 2009

Helmut Graeb, Daniel Mueller, Ulf Schlichtmann
Pareto-Optimierung analoger Schaltungen mit Parametertoleranzen
In: ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG)
April 2008

Jun Zou, Daniel Mueller, Helmut Graeb, Ulf Schlichtmann
Optimization of SC ΣΔ Modulators based on Worst-Case-Aware Pareto-Optimal Fronts
In: IEEE Custom Integrated Circuits Conference (CICC)
September 2007

Helmut Graeb, Daniel Mueller, Ulf Schlichtmann
Pareto Optimization of Analog Circuits considering Variability
In: European Conference on Circuit Theory and Design (ECCTD)
August 2007

Daniel Mueller, Helmut Graeb, Ulf Schlichtmann
Trade-Off Design of Analog Circuits using Goal Attainment and Wave Front Sequential Quadratic Programming
In: Design, Automation and Test in Europe (DATE)
April 2007

Jun Zou, Daniel Mueller, Helmut Graeb, Ulf Schlichtmann
Pareto-Front Computation and Automatic Sizing of CPPLLs
In: IEEE International Symposium on Quality Electronic Design
March 2007

Helmut Graeb, Jun Zou, Daniel Mueller, Ulf Schlichtmann
Hierarchische Optimierung einer Phasenregelschaltung
In: ASIM/GI-Fachgruppentagung Simulation technischer Systeme/Grundlagen und Methoden in Modellbildung und Simulation
February 2007

Daniel Mueller, Helmut Graeb, Ulf Schlichtmann
Optimierung analoger Schaltungsbloecke mittels Pareto-Wellenfront-Optimierung
In: ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG)
September 2006

Daniel Mueller, Guido Stehr, Helmut Graeb, Ulf Schlichtmann
Fast Evaluation of Analog Circuit Structures by Polytopal Approximations
In: IEEE International Symposium on Circuits and Systems (ISCAS)
2006

Jun Zou, Daniel Mueller, Helmut Graeb, Ulf Schlichtmann
A CPPLL Hierarchical Optimization Methodology Considering Jitter, Power and Locking Time
In: ACM/IEEE Design Automation Conference (DAC)
2006

Daniel Mueller, Guido Stehr, Helmut Graeb, Ulf Schlichtmann
Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen
Informatik 2005, Beiträge der 35 Jahrestagung der Gesellschaft für Informatik 1, 334-338
September 2005

Jun Zou, Daniel Mueller, Helmut Graeb, Ulf Schlichtmann, Eckhard Hennig, Ralf Sommer
Fast Automatic Sizing of a Charge Pump Phase-Locked Loop based on Behavioral Models
In: IEEE International Behavioral Modeling and Simulation Conference
September 2005

Daniel Mueller, Guido Stehr, Helmut Graeb, Ulf Schlichtmann
Deterministic Approaches to Analog Performance Space Exploration (PSE)
In: ACM/IEEE Design Automation Conference (DAC)
June 2005

Florian Krug, Daniel Mueller, Peter Russer
Signal Processing Strategies With the TDEMI Measurement System
IEEE Transactions on Instrumentation and Measurement 53(5)
October 2004

Florian Krug, Tobias Hermann, Daniel Mueller, Jan Waldmann, Martin Aidam, Peter Russer
Strategies for Precompliance Measurements using the TDEMI measurement system
August 2003

Florian Krug, Daniel Mueller, Peter Russer
Statistical Physical Noise Behavior Analysis of the Time Domain EMI Measurement System
In: IEEE AP-S International Symposium on Antennas and Propagation
June 2003