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Sign-off timing verificationH. Gräb
Werkstudent Cadence im Bereich ITH. Gräb
VLSI lab tutor (contatct Hu
Integration of a Fully Programmable Valve Array with CoSyn for Reliable and efficient Single-Cell AnalysisY. Moradi

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SRAM Array Design-Methodology for Robustness against Aging and Process VariationsA. ListlMrudula Yedavally
Enhancing Cloud Columba (Web Design)T.-M. TsengFan Fan