Angebotene Arbeiten

Sign-off timing verificationH. Gräb
Werkstudent Cadence im Bereich ITH. Gräb
VLSI lab tutor (contatct Hu
Control layer optimization for flow-based microfluidic routing fabricY. Moradi
Integration of a Fully Programmable Valve Array with CoSyn for Reliable and efficient Single-Cell AnalysisY. Moradi

In Bearbeitung

SRAM Array Design-Methodology for Robustness against Aging and Process VariationsA. ListlMrudula Yedavally