Masterarbeiten

Themen für Masterarbeiten mit einer vorgesehenen Dauer von 6 Monaten.

Angebotene Arbeiten

ThemaBetreuerGebiet
Test Generation for Digital Circuits with Wave-PipeliningB. LiDigitalentwurf
RTL Accurate Soft-Error Vulnerability Assessment for RISC-V based Pulpino-SoCU. SharifDigitalentwurf
Advanced RISC-V ISS Coverage Metrics Solutions (at MinRES)D. Müller-G.High-Level-Modellierung
New ways of Detection and Handling of Soft Errors in Embedded Control SystemsD. Müller-G.High-Level-Modellierung
Timing Models for Ultra-fast Host-compiled Simulation of Embedded SoftwareD. Müller-G.High-Level-Modellierung
different topics on biochip testingA. Bernardini
Classification of Blood Cells using Deep Learning MethodsD. Müller-G.
Modeling RISC-V for ETISSD. Müller-G.
Multi-Level Fault Simulation for RISC V implemented in C++D. Müller-G.
Non-intrusive Runtime Monitoring of MPSoCs in HWM. Mettler
Power-Down Synthesis for Hierarchical Analog CircuitsM. Neuner
Enabling Full Automation for Code Generation from ISA DescriptionsR. Stahl
Static Code Analysis Topics with C++R. Stahl
Control flow protection in embedded SWU. Sharif
Porting Robot-Arm Embedded SW on Pulpino-SoCU. Sharif
Porting Segway Embedded SW on Pulpino SoCU. Sharif
Control layer optimization for flow-based microfluidic routing fabricY. Moradi

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In Bearbeitung

ThemaBetreuerStudent
Testing of different optimization algorithms for solving the initial sizing problem of analog circuitsI. AbelBharatendu Soumil
On-Chip Aging Sensors to Monitor NBTI Effect in Nano-Scale SRAMA. ListlShreyas Nittur Prasannakumar
Development of HW prototype for next generation magnetic sensorD. Müller-G.Yanqin Li
Implementation of a Light Fence for Roboter-Human InteractionD. Müller-G.Christian Bernhardt
Integration of Driver-in-loop Simulator for Testing ADAS/Autonomous Driving FeaturesD. Müller-G.Sultan Haider
Performance acceleration of CNN using HW acceleration on FPGAs @NXPD. Müller-G.Seifeddine AYADI
Emulation of an ASIC Temperature Monitor System for FPGA PrototypingM. MettlerArooj Asif
Deep Code Profiling for 5G Communication TesterR. StahlPramod Tikare Muralidhara
Improve Source-Binary Mapping for Host-Compiled Simula- tion with OptimizationsR. StahlAyush Patel
RTL Register Interface Generation for Optimized HW/SW-InterfacesR. StahlJawad Tariq
Switch Design for Microfluidic Large-Scale IntegrationT.-M. TsengYanlu Ma
Fault-Tolerant Routing of Barcoding Droplets in Single-Cell Analysis Using Fully Programmable Valve ArraysY. MoradiPreetha Palanivel