Publikationen

2018


Li Zhang, Bing Li, Bei Yu, David Z. Pan, Ulf Schlichtmann
TimingCamouflage: Improving Circuit Security against Counterfeiting by Unconventional Timing
In: Design, Automation and Test in Europe (DATE)
March 2018

Yasamin Moradi, Mohamed Ibrahim, Krishnendu Chakrabarty, Ulf Schlichtmann
Fault-tolerant valve-based microfluidic routing fabric for droplet barcoding in single-cell analysis
In: Proceedings of the Design, Automation and Test in Europe (DATE)
March 2018

Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen, Helmut Graeb, Ulf Schlichtmann
On Enabling Diagnosis for 1-Pin Test Fails in an Industrial Flow
In: Asia and South Pacific Design Automation Conference (ASP-DAC)
January 2018

Tsun-Ming Tseng, Mengchu Li, Daniel Nestor Freitas, Travis McAuley, Bing Li, Tsung-Yi Ho, Ismail Emre Araci, Ulf Schlichtmann
Columba 2.0: A Co-Layout Synthesis Tool for Continuous-Flow Microfluidic Biochips (pdf)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2018

Li Zhang, Bing Li, Jinglan Liu, Yiyu Shi, Ulf Schlichtmann
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning (pdf)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2018

2017


Mohamed Ibrahim, Aditya Sridhar, Krishnendu Chakrabarty, Ulf Schlichtmann
Sortex: Efficient Timing-Driven Synthesis of Reconfigurable Flow-Based Biochips for Scalable Single-Cell Screening
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 2017

Elisabeth Glocker
Thermisches Verhalten und emuliertes online Temperatur-Monitorsystem für das FPGA-Prototyping von Multiprozessor-Architekturen
PhD Thesis
Technische Universität München
November 2017

Daniel Mueller-Gritschneder, Martin Dittrich, Marc Greim, Keerthikumara Devarajegowda, Wolfgang Ecker, Ulf Schlichtmann
The Extendable Translating Instruction Set Simulator (ETISS) interlinked with an MDA Framework for fast RISC Prototyping
In: IEEE International Symposium on Rapid System Prototyping (RSP)
October 2017

Bing Li, Ulf Schlichtmann
Reliability‐aware Synthesis and Fault Test of Fully Programmable Valve Arrays (FPVAs)
In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
October 2017

Maximilian Neuner, Michael Zwerger, Helmut Graeb
Power-Down-Synthese für analoge Schaltungen
ZuE 2017; 9. ITG/GMM/GI-Fachtagung Zuverlässigkeit und Entwurf
September 2017

Baris Yigit, Li Zhang, Bing Li, Yiyu Shi, Ulf Schlichtmann
Application of Machine Learning Methods in Post‐Silicon Yield Improvement
In: IEEE International System on Chip Conference (SOCC)
September 2017

Jinglan Liu, Yukun Ding, Jianlei Yang, Ulf Schlichtmann, Yiyu Shi
Generative Adversarial Network Based Scalable On-chip Noise Sensor Placement
In: IEEE International System on Chip Conference (SOCC)
September 2017

Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann
An Efficient Two-Phase ILP-Based Algorithm for Precise CMOS RFIC Layout Generation (pdf)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36(8), 1313-1326
August 2017

Tsun-Ming Tseng
Design Automation for Continuous-Flow Microfluidic Biochips (pdf)
PhD Thesis
Technische Universität München
August 2017

Sebastian Sievert
Development of Analytical Behavioral Models for Digitally Controlled Edge Interpolator (DCEI) based Digital-to-Time Converter (DTC) Circuits
PhD Thesis
Technische Universität München
August 2017

Andreas Herrmann, Christof Hielscher, Alexander Mueller, Gisbert Hoelzer, Helmut Graeb
Realistic Worst-Case for MEMS
In: Frontiers in Analog Circuit (FAC) Synthesis and Verification
July 2017

Florin Burcea, Andreas Herrmann, Helmut Graeb
Towards MEMS-IC Robustness Optimization
In: Frontiers in Analog Circuit (FAC) Synthesis and Verification
July 2017

Daniel Mueller-Gritschneder, Andreas Gerstlauer
Host-Compiled Simulation
In: Handbook of Hardware/Software Codesign
Springer Netherlands, June 2017

Mengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
Component-Oriented High-Level Synthesis for Continuous-Flow Microfluidics Considering Hybrid-Scheduling (pdf)
In: ACM/IEEE Design Automation Conference (DAC)
June 2017

Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann
Transport or Store? Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage
In: ACM/IEEE Design Automation Conference (DAC)
June 2017

Florin Burcea, Andreas Herrmann, Aditya Gupta, Helmut Graeb
A New Robustness Optimization Methodology for MEMS-IC Systems
In: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
June 2017

Andreas Herrmann, Christof Hielscher, Alexander Mueller, Gisbert Hoelzer, Helmut Graeb
Realistic Worst-Case Parameter Sets for MEMS Technologies
In: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
June 2017

Ulf Schlichtmann
Frontiers of timing
In: ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)
June 2017

Elisabeth Glocker, Qingqing Chen, Ulf Schlichtmann, Doris Schmitt Landsiedel
Emulation of an ASIC Power and Temperature Monitoring System (eTPMon) for FPGA Prototyping
Microprocessors and Microsystems 50, 90--101
May 2017

Dimo Martev, Sven Hampel, Ulf Schlichtmann
Methodology for automated phase noise minimization in RF circuit interconnect trees
In: IEEE International Symposium on Circuits and Systems (ISCAS)
May 2017

Dimo Martev, Sven Hampel, Ulf Schlichtmann
A Method for Phase Noise Analysis of RF Circuits
In: Great Lakes Symposium on VLSI (GLVLSI)
May 2017

Nai-Chen Chen, Pang-Yen Chou, Helmut Graeb, Mark Po-Hung Lin
High-Density MOM Capacitor Array with Novel Mortise-Tenon Structure for Low-Power SAR ADCs
In: Design, Automation and Test in Europe (DATE)
March 2017

Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann
Testing Microfluidic Fully Programmable Valve Arrays (FPVAs) (pdf)
In: Design, Automation and Test in Europe (DATE)
March 2017

Mohamed Ibrahim, Krishnendu Chakrabarty, Ulf Schlichtmann
CoSyn: Efficient single-cell analysis using a hybrid microfluidic platform
In: Design, Automation & Test in Europe Conference & Exhibition (DATE)
March 2017

Yong Hu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
A Model-based Framework For Networks-on-Chip Design Space Exploration
2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISTECS)
January 2017

Qin Wang, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai
Hamming-Distance-Based Valve-Switching Optimization for Control Multiplexing in Flow-Based Microfluidic Biochip (pdf)
In: IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC)
January 2017

Michael Zwerger
Verification and Synthesis of Analog Power-Down Circuits
PhD Thesis
Technische Universität München
January 2017

Michael Zwerger, Maximilian Neuner, Helmut Graeb
Analog Power-Down Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2017

Pang-Yen Chou, Nai-Chen Chen, Mark Po-Hung Lin, Helmut Graeb
Matched-Routing Common-Centroid 3-D MOM Capacitors for Low-Power Data Converters
IEEE Transactions on Very Large Scale Integration Systems (TVLSI)
2017

2016


Tsun-Ming Tseng, Bing Li, Mengchu Li, Tsung-Yi Ho, Ulf Schlichtmann
Reliability-aware Synthesis with Dynamic Device Mapping and Fluid Routing for Flow-based Microfluidic Biochips (pdf)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35(12), 1981-1994
December 2016

Santiago Pagani, Lars Bauer, Qingqing Chen, Elisabeth Glocker, Frank Hannig, Andreas Herkersdorf, Heba Khdr, Anuj Pathania, Ulf Schlichtmann, Doris Schmitt-Landsiedel, Mark Sagi, Ericles Sousa, Philipp Wagner, Volker Wenzel, Thomas Wild, Jörg Henkel
Dark silicon management: an integrated and coordinated cross-layer approach
it - Information Technology 58(6)
December 2016

Daniel Mueller-Gritschneder, Marc Greim, Ulf Schlichtmann
Safety Evaluation based on Virtual Prototypes: Fault Injection with Multi-level Processor Models
In: International Symposium on Integrated Circuits (ISIC)
December 2016

Jie Wu, Ulf Schlichtmann, Yiyu Shi
On the measurement of power grid robustness under load uncertainties
2016 IEEE International Conference on Smart Grid Communications (SmartGridComm), 218-223
November 2016

Qin Wang, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li, Ulf Schlichtmann, Yici Cai
Control-Fluidic CoDesign for Paper-Based Digital Microfluidic Biochips (pdf)
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 2016

Robert Wille, Bing Li, Ulf Schlichtmann, Rolf Drechsler
From Biochips to Quantum Circuits: Computer-Aided Design for Emerging Technologies
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 2016

Li Zhang, Bing Li, Ulf Schlichtmann
PieceTimer: a holistic timing analysis framework considering setup/hold time interdependency a piecewise model (pdf)
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 2016

Alessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann
Where Formal Verification Can Help in Functional Safety Analysis
In: Proceedings of the 35th International Conference on Computer-Aided Design
November 2016

Petra R. Maier, Veit B. Kleeberger, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Fault Injection at Host-Compiled Level with Static Fault Set Reduction for SoC Firmware Robustness Testing
In: International conference on Hardware/Software codesign and system synthesis (CODES+ISSS)
October 2016

Maximilian Neuner, Michael Zwerger, Helmut Graeb
Power-Down Schematic Synthesis for Analog/Mixed-Signal Circuits
15. ITG/GMM-Fachtagung (Analog 2016)
September 2016

Alessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann
Efficient handling of the fault space in functional safety analysis utilizing formal methods
In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
September 2016

André Lange
Non-Gaussian Correlated Multivariate Modeling for Variability Abstraction in Integrated Circuit Analysis
PhD Thesis
September 2016

Mark Po-Hung Lin, Po-Hsun Chang, Shuenn-Yuh Lee, Helmut E. Graeb
DeMixGen: Deterministic Mixed-signal Layout Generation with Separated Analog and Digital Signal Paths
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
August 2016

Shushanik Karapetyan, Veit B. Kleeberger, Ulf Schlichtmann
FinFET Based Product Performance: Modeling and Evaluation of Standard Cells in FinFET Technologies
Microelectronics Reliability 61, 30-34
June 2016

Michael Zwerger, Gaurav Shrivastava, Helmut Graeb
Power-Down Synthesis for Analog Circuits including Switch Sizing
In: Symbolic Methods and Applications in Circuit Design (SMACD)
June 2016

Dimo Martev, Sven Hampel, Ulf Schlichtmann
Fully synthesized time-to-digital converter for cellular transceivers
In: Second International Conference on Event-based Control, Communication, and Signal Processing (EBCCSP)
June 2016

Tsun-Ming Tseng, Mengchu Li, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
Columba: Co-Layout Synthesis for Continuous-Flow Microfluidic Biochips (pdf)
In: ACM/IEEE Design Automation Conference (DAC)
June 2016

Li Zhang, Bing Li, Ulf Schlichtmann
EffiTest: Efficient delay test and statistical prediction for configuring post-silicon tunable buffers (pdf)
In: ACM/IEEE Design Automation Conference (DAC)
June 2016

Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann
Novel CMOS RFIC Layout Generation with Concurrent Device Placement and Fixed-Length Microstrip Routing (pdf)
In: ACM/IEEE Design Automation Conference (DAC)
June 2016

Florin Burcea, Husni Habal, Helmut Graeb
Procedural Capacitor Placement in Differential Charge-Scaling Converters by Nonlinearity Analysis
In: ACM/IEEE Design Automation Conference (DAC)
June 2016

Florin Burcea, Husni Habal, Helmut Graeb
A Novel Analytical Model for the Static Behavior of a Monotonic-Switching Charge-Scaling ADC
In: Ph.D. Research in Microelectronics and Electronics (PRIME)
June 2016

Dimo Martev, Sven Hampel, Ulf Schlichtmann
Synthesis-based methodology for high-speed multi-modulus divider
In: 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD
June 2016

Munish Jassi, Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Hardware-Accelerated Software Libraries Drivers Generation for IP-Centric SoC Designs
In: Great Lakes Symposium on VLSI (GLS-VLSI)
May 2016

Li Zhang, Alexandra Listl, Bing Li, Ulf Schlichtmann
Effizienter Verzögerungstest zur Optimierung der Taktfrequenz einer Schaltung durch nach der Fertigung konfigurierbare Puffer
In: edaWorkshop
May 2016

Florin Burcea, Husni Habal, Helmut Graeb
Eine Methode zur Platzierung der Kapazitäten in differenziellen Ladungsumverteilungs-Wandlern durch Analyse von Nichtlinearitäten
In: edaWorkshop
May 2016

Petra R. Maier, Veit B. Kleeberger, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Fehlerinjektion auf Unit-Ebene zur Robustheitsverifikation eingebetteter Software
In: edaWorkshop
May 2016

Anja von Beuningen, Ulf Schlichtmann
PLATON: A Force-Directed Placement Algorithm for 3D Optical Networks-on-Chip
In: ACM/SIGDA International Symposium on Physical Design (ISPD)
April 2016

Pang-Yen Chou, Mark Po-Hung Lin, Helmut Graeb
An integrated placement and routing for ratioed capacitor array based on ILP formulation
In: VLSI Design, Automation and Test (VLSI-DAT)
April 2016

Ulf Schlichtmann
The next frontier in IC design: Determining (and optimizing) robustness and resilience of integrated circuits and systems
2016 China Semiconductor Technology International Conference (CSTIC), 1-4
March 2016

Mengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
Sieve-valve-aware Synthesis of Flow-based Microfluidic Biochips Considering Specific Biological Execution Limitations (pdf)
In: Design, Automation and Test in Europe (DATE)
March 2016

Li Zhang, Bing Li, Ulf Schlichtmann
Sampling-based buffer insertion for post-silicon yield improvement under process variability (pdf)
In: Design, Automation and Test in Europe (DATE)
March 2016

Daniel Tille, Daniel Thangaraj Stanley, Ulrike Pfannkuchen, Helmut Graeb, Ulf Schlichtmann
On Improving Test Point Insertion using Fault Classification Results
In: ITG/GMM/GI Testmethoden und Zuverlässigkeit von Schaltungen und Systemen
March 2016

Munish Jassi, Yong Hu, Jian Lyu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
GRIP: Graph-Rewriting-Based IP-Integration - An EDA Tool for Software Defined SoC Design
In: Design, Automation and Test in Europe (DATE) University Booth
March 2016

André Lange, Christoph Sohrmann, Roland Jancke, Joachim Haase, Binjie Cheng, Asen Asenov, Ulf Schlichtmann
Multivariate Modeling of Variability Supporting Non-Gaussian and Correlated Parameters
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35(2)
February 2016

Petra R. Maier, Daniel Mueller-Gritschneder, Ulf Schlichtmann, Veit B. Kleeberger
Embedded Software Reliability Testing by Unit-Level Fault Injection
In: IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC)
January 2016

Ulf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang, Bing Li
Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits (pdf)
In: IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC)
January 2016

Husni Habal, Helmut Graeb
A Step-Accurate Model for the Trapping and Release of Charge Carriers Suitable for the Transient Simulation of Analog Circuits
Journal of Microelectronics Reliability
2016
Available online 26 January 2016, ISSN 0026-2714, http://dx.doi.org/10.1016/j.microrel.2016.01.001.

Bogdan Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello
Optimization of Transient-Fault Injection Through Analysis of Simulation Traces
edaWorkshop, 1--6
2016

Bogdan Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello
Gate-Level-Accurate Fault-Effect Analysis at Virtual-Prototype Speed
ERCIM/EWICS/ARTEMIS Workshop on ``Dependable Embedded and Cyber-physical Systems and Systems-of-Systems'' (DECSoS'16), 1--13
2016

Bogdan Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello
Efficient Checkpointing-Based Safety-Verification Flow Using Compiled-Code Simulation
Digital System Design (DSD), 2016 Euromicro Conference on, 1--8
2016

Bogdan Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello
Fault-Effect Analysis on Multiple Abstraction Levels in Hardware Modeling
DVCon USA, 1--12
2016

Bogdan Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello
Fault-Effect Analysis on System-Level Hardware Modeling using Virtual Prototypes
Forum on Specification and Design Languages (FDL), 1--7
2016

Bogdan Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello
Speeding up Safety Verification by Fault Abstraction and Simulation to Transaction Level
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 1--6
2016

Bogdan Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello
Safety-Verification Flow Sporting Gate-Level Accuracy and Near Virtual-Prototype Speed
DVCon Europe, 1--8
2016

Moomen Chaari, Wolfgang Ecker, Bogdan Andrei Tabacaru, Cristiano Novello, Thomas Kruse
Linking Model-Based Safety Analysis to Fault Injection and Simulation in Virtual Prototypes
2016

Moomen Chaari, Wolfgang Ecker, Bogdan Andrei Tabacaru
Towards Cross-Domain and Multi-Level Dependability Analysis Through Metamodeling and Code Generation
2016

Wolfgang Ecker, Johannes Schreiner
Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler and more efficient hardware generators
In: 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
2016

Johannes Schreiner, Rainer Findenig, Wolfgang Ecker
Design centric modeling of digital hardware
In: High Level Design Validation and Test Workshop (HLDVT), 2016 IEEE International
2016

Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello, Bogdan Andrei Tabacaru
Transformation of Failure Propagation Models into Fault Trees for Safety Evaluation Purposes
In: Dependable Systems and Networks Workshop, 2016 46th Annual IEEE/IFIP International Conference on
2016

2015


Tsun-Ming Tseng, Bing Li, Ulf Schlichtmann, Tsung-Yi Ho
Storage and Caching: Synthesis of Flow-based Microfluidic Biochips (pdf)
IEEE Design and Test
December 2015

Anja von Beuningen, Luca Ramini, Davide Bertozzi, Ulf Schlichtmann
PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer
ACM Journal on Emerging Technologies in Computing Systems (JETC) 12(4), 44:1--44:28
December 2015

Michael Zwerger, Pantelis-Rafail Vlachas, Helmut Graeb
A Fast Analytical Approach for Static Power-Down Mode Analysis
In: IEEE International Conference on Electronics, Circuits, & Systems (ICECS)
December 2015

Kun Lu
Performance Estimation in HW/SW Co-simulation
PhD Thesis
Technische Universität München
December 2015

Bing Li, Ulf Schlichtmann
Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements (pdf)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
November 2015

Michael Zwerger, Maximilian Neuner, Helmut Graeb
Power-Down Circuit Synthesis for Analog/Mixed-Signal
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 2015

Shushanik Karapetyan, Ulf Schlichtmann
Aging Aware Timing Analysis Incorporated into a Commercial STA Tool
In: REES Workshop
November 2015

Chia-Yu Wu, Helmut Graeb, Jiang Hu
A Pre-search Assisted ILP Approach to Analog Integrated Circuit Routing
In: IEEE International Conference on Computer Design (ICCD)
October 2015

Bing Li, Tsun-Ming Tseng, Tsung-Yi Ho, Ulf Schlichtmann
Design Automation for Microfluidic Biochips Considering Efficiency and Reliability
In: MikroSystemTechnik Kongress
October 2015

Martin Barke, Ulf Schlichtmann
A Cross-Layer Approach to Measure the Robustness of Integrated Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Cross-Layer System Design and Regular Papers 12(3)
September 2015

Munish Jassi, Benjamin Bordes, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Automation of FPGA Performance Monitoring and Debugging Using IP-XACT and Graph-Grammars
In: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
September 2015

Alessandro Bernardini, Ulf Schlichtmann
Symbolic Fault Modeling and Model Counting for the Identification of Critical Gates in Digital Circuits
In: ZuE 2015; 8. GMM/ITG/GI-Symposium Reliability by Design; Proceedings of
September 2015

Qingqing Chen, Ulrich Rührmair, Spoorthy Narayana, Uzair Sharif, Ulf Schlichtmann
MWA Skew SRAM Based SIMPL Systems for Public-Key Physical Cryptography
In: Proceedings of the 8th International Conference on Trust & Trustworthy Computing (TRUST 2015)
August 2015

Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing (pdf)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34(6), 1000-1013
June 2015

Michael Glaß, Hananeh Aliee, Liang Chen, Mojtaba Ebrahimi, Faramarz Khosravi, Veit B. Kleeberger, Alexandra Listl, Daniel Mueller-Gritschneder, Fabian Oboril, Ulf Schlichtmann, Mehdi B. Tahoori, Jürgen Teich, Norbert Wehn, Christian Weis
Application-aware cross-layer reliability analysis and optimization
it – Information Technology 2015 57, 159–169
June 2015

Munish Jassi, Daniel Mueller-Gritschneder, Ulf Schlichtmann
GRIP: Grammar-Based IP Integration and Packaging for Acceleration-Rich SoC Designs
In: ACM/IEEE Design Automation Conference (DAC)
June 2015

Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
Reliability-aware Synthesis for Flow-based Microfluidic Biochips by Dynamic-device Mapping (pdf)
In: ACM/IEEE Design Automation Conference (DAC)
June 2015

Ericles Sousa, Frank Hannig, Jürgen Teich, Qingqing Chen, Ulf Schlichtmann
Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays
In: Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES 2015)
June 2015

Elisabeth Glocker, Qingqing Chen, Asheque Zaidi, Ulf Schlichtmann, Doris Schmitt-Landsiedel
Emulation of an ASIC Power and Temperature Monitor System for FPGA Prototyping
In: Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015)
June 2015

Vladimir Todorov
On Application-Specific Network-on-Chip Synthesis and On-Chip Trace and Debug
PhD Thesis
Technische Universität München
June 2015

Marc Greim, Daniel Mueller-Gritschneder, Ulf Schlichtmann
C++ Processor Models for Accelerated Multi-level Error Effect Simulation
In: edaWorkshop
May 2015

Bing Li, Ulf Schlichtmann
Evaluation of circuit performance and configuration reduction considering post-silicon clock skew tuning
In: edaWorkshop
May 2015

Shushanik Karapetyan, Ulf Schlichtmann
Integrating Aging Aware Timing Analysis into a Commercial STA Tool
In: VLSI Design, Automation and Test (VLSI-DAT)
April 2015

Michael Zwerger, Helmut Graeb
Detection of Asymmetric Aging-Critical Voltage Conditions in Analog Power-Down Mode
In: Design, Automation and Test in Europe (DATE)
March 2015

Oliver Bringmann, Wolfgang Ecker, Andreas Gerstlauer, Ajay Goyal, Daniel Mueller-Gritschneder, Prasanth Sasidharan, Simranjit Singh
The Next Generation of Virtual Prototyping: Ultra-fast Yet Accurate Simulation of HW/SW Systems
In: Design, Automation and Test in Europe (DATE)
March 2015

Rohit Kumar, Bing Li, Yiren Shen, Ulf Schlichtmann, Jiang Hu
Timing Verification for Adaptive Integrated Circuits
In: Design, Automation and Test in Europe (DATE)
March 2015

Anja von Beuningen, Ulf Schlichtmann
A Force-Directed Placement Algorithm for 3D Optical Networks-on-Chip
In: International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS)
March 2015

Ulf Schlichtmann
Beyond GORDIAN and Kraftwerk: EDA Research at TUM
In: International Symposium on Physical Design (ISPD’15)
March 2015

Daniel Mueller-Gritschneder
VHDL Code Generation from IP-Xact using the Eclipse Modeling Framework (EMF)
In: Design and Verification Conference and Exhibition (DVCon) Tutorials
March 2015

Ulrich Rührmair
Disorder-Based Security Hardware
PhD Thesis
Technische Universität München
March 2015

Yong Hu, Daniel Mueller-Gritschneder, Sepulveda, M.J., Gogniat, G., Ulf Schlichtmann
Automatic ILP-based Firewall Insertion for Secure Application-Specific Networks-on-Chip
In: Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC), 2015 Ninth International Workshop on
January 2015

Veit B. Kleeberger
Resilient Cross-Layer Design of Digital Integrated Circuits
PhD Thesis
Technische Universität München
January 2015

Christian Michael Pehl, Matthias Hiller, Helmut Graeb
Efficient Evaluation of Physical Unclonable Functions Using Entropy Measures
Journal of Circuits, Systems, and Computers
2015

Florin Burcea, Husni Habal, Helmut Graeb
A New Chessboard Placement and Sizing Method for Capacitors in a Charge-Scaling DAC by Worst-Case Analysis of Nonlinearity
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on PP(99), 1-1
2015

Arpad Bürmen, Husni Habal
Computing Worst-Case Performance and Yield of Analog Integrated Circuits by Means of Mesh Adaptive Direct Search
Informacije MIDEM, Journal of Microelectronics, Electronic Components and Materials 45(2), 160-170
2015
http://www.midem-drustvo.si/Journal%20papers/MIDEM_45%282015%292p160.pdf http://www.midem-drustvo.si/journal/Issues.aspx

2014


Veit B. Kleeberger, Christian Weis, Ulf Schlichtmann, Norbert Wehn
Circuit Resilience Roadmap
In: Circuit Design for Reliability, Chap. 7
Ed.: Ricardo Reis, Yu Cao, and Gilson Wirth
Springer, December 2014

Michael Pehl, Akshara Ranjit Punnakkal, Matthias Hiller, Helmut Graeb
Advanced Performance Metrics for Physical Unclonable Functions
In: International Symposium on Integrated Circuits (ISIC)
December 2014

Dip Goswami, Daniel Mueller-Gritschneder, Basten Twan, Ulf Schlichtmann, Samarjit Chakraborty
Fault-tolerant Embedded Control Systems for Unreliable Hardware
In: International Symposium on Integrated Circuits (ISIC)
December 2014

Daniel Mueller-Gritschneder, Petra R. Maier, Marc Greim, Ulf Schlichtmann
SystemC-based Multi-level Error Injection for the Evaluation of Fault-tolerant Systems
In: International Symposium on Integrated Circuits (ISIC)
December 2014

Martin Barke
Aging Aware Robustness Validation of Digital Integrated Circuits
PhD Thesis
Technische Universität München
December 2014

Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann
Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 33(10), 1503-1516
October 2014

Veit B. Kleeberger, Martin Barke, Christoph Werner, Doris Schmitt-Landsiedel, Ulf Schlichtmann
A Compact Model for NBTI Degradation and Recovery under Use-Profile Variations and its Application to Aging Analysis of Digital Integrated Circuits
Microelectronics Reliability 54(6-7), 1083-1089
June 2014

Dominik Lorenz, Martin Barke, Ulf Schlichtmann
Monitoring of Aging in Integrated Circuits by Identifying Possible Critical Paths
Microelectronics Reliability 54(6-7), 1075-1082
June 2014

Andreas Herkersdorf, Hananeh Aliee, Michael Engel, Michael Glaß, Christina Gimmler-Dumont, Jörg Henkel, Veit B. Kleeberger, Michael A. Kochte, Johannes M. Kühn, Daniel Mueller-Gritschneder, Sani R. Nassif, Holm Rauchfuss, Wolfgang Rosenstiel, Ulf Schlichtmann, Muhammad Shafique, Mehdi B. Tahoori, Jürgen Teich, Norbert Wehn, Christian Weis, Hans-Joachim Wunderlich
Resilience Articulation Point (RAP): Cross-layer Dependability Modeling for Nanometer System-on-chip Resilience
Microelectronics Reliability 54(6-7), 1066-1074
June 2014

Martin Barke, Michael Kaergel, Markus Olbrich, Ulf Schlichtmann
Robustness Measurement of Integrated Circuits and its Adaptation to Aging Effects
Microelectronics Reliability 54(6-7), 1058-1065
June 2014

Veit B. Kleeberger, Petra R. Maier, Ulf Schlichtmann
Workload- and Instruction-Aware Timing Analysis - The missing Link between Technology and System-level Resilience
In: ACM/IEEE Design Automation Conference (DAC)
June 2014

J. H. Oetjens, N. Bannow, M. Becker, Oliver Bringmann, A. Burger, Moomen Chaari, Samarjit Chakraborty, Rolf Drechsler, Wolfgang Ecker, K. Gr\, Th. Kruse, C. Kuznik, H. M. Le, A. Mauderer, W. M\, Daniel Mueller-Gritschneder, F. Poppen, H. Post, S. Reiter, Wolfgang Rosenstiel, S. Roth, Ulf Schlichtmann, A. von Schwerin, B. A. Tabacaru, Alexander Viehl
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges
In: Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference
June 2014

Michael Linder, Alfred Eder, Klaus Oberländer, Ulf Schlichtmann
An Analysis of Industrial SRAM Test Results—A Comprehensive Study on Effectiveness and Classification of March Test Algorithms
IEEE Design and Test
May 2014

Anja Boos, Luca Ramini, Davide Bertozzi, Ulf Schlichtmann
Ein Platzier- und Verdrahtungsalgorithmus für Optische Networks-on-Chip zur Minimierung der Einfügedämpfung
In: edaWorkshop
May 2014

Veit B. Kleeberger, Magdalena Dorfner, Ulf Schlichtmann
Evaluation of Sequential Circuit Resilience in Early Design Stages
In: edaWorkshop
May 2014

Pang-Yen Chou, Helmut Graeb
Platzierung von Kapazitäts-Arrays: ein konstruktiver Ansatz
In: edaWorkshop
May 2014

Elisabeth Glocker, Qingqing Chen, Asheque M. Zaidi, Ulf Schlichtmann, Doris Schmitt-Landsiedel
Emulated ASIC Power and Temperature Monitor System for FPGA Prototyping of an Invasive MPSoC Computing Architecture
In: Proceedings of the 1st Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014)
May 2014

Ulf Schlichtmann, Veit B. Kleeberger, Jacob A. Abraham, Adrian Evans, Christina Gimmler-Dumont, Michael Glaß, Andreas Herkersdorf, Sani R. Nassif, Norbert Wehn
Connecting Different Worlds – Technology Abstraction for Reliability-Aware Design and Test
In: Design, Automation and Test in Europe (DATE)
March 2014

Felix Miller, Vladimir Todorov, Thomas Wild, Daniel Mueller-Gritschneder, Andreas Herkersdorf, Ulf Schlichtmann
A TSV-Property-aware Synthesis Method for Application-Specific 3D-NoCs Design
In: Design Automation and Test in Europe (DATE), Friday Workshop on 3D Integration
March 2014

Elisabeth Glocker, Qingqing Chen, Asheque Zaidi, Ulf Schlichtmann, Doris Schmitt-Landsiedel
Emulierung eines ASIC-Leistungsverbrauchs- und Temperaturmonitorsystems für FPGA-Prototyping eines ressourcengewahren Computersystems
In: 16. Workshop Analogschaltungen
February 2014

Elisabeth Glocker, Srinivas Boppu, Qingqing Chen, Ulf Schlichtmann, Jürgen Teich, Doris Schmitt-Landsiedel
Temperature Modeling and Emulation of an ASIC Temperature Monitor System for Tightly-Coupled Processor Arrays (TCPAs)
Advances in Radio Science 12, 103--109
2014

2013


Anja Boos, Luca Ramini, Ulf Schlichtmann, Davide Bertozzi
PROTON: An Automatic Place-and-Route Tool for Optical Networks-on-Chip
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 2013

Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
Post-route alleviation of dense meander segments in high-performance printed circuit boards (pdf)
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 2013

Veit B. Kleeberger, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Technology-Aware System Failure Analysis in the Presence of Soft Errors by Mixture Importance Sampling
In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
October 2013

Michael Linder
Test Set Optimization for Industrial SRAM Testing
PhD Thesis
Technische Universität München
October 2013

Husni Habal, Helmut Graeb
Analyse analoger Schaltungseigenschaften bei Kurz- und Langzeitalterungseffekten
In: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf
September 2013

Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
Iterative Refinement of Dense Meander Segments in High-speed Printed Circuit Boards
In: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf
September 2013

Veit B. Kleeberger, Helmut Graeb, Ulf Schlichtmann
Modellierung und Evaluierung von Standardzellen in FinFET-Technologie
In: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf
September 2013

Michael Zwerger, Helmut Graeb
Verification of the power-down mode of analog circuits by structural voltage propagation
Analog Integrated Circuits and Signal Processing
August 2013
DOI 10.1007/s10470-013-0107-x

Veit B. Kleeberger, Petra Maier, Ulf Schlichtmann
Ein stochastisches Modell zur Beschreibung von Signalen in digitalen Schaltungen basierend auf quadratischer Optimierung
Advances in Radio Science 11
July 2013

Veit B. Kleeberger, Christina Gimmler-Dumont, Christian Weis, Andreas Herkersdorf, Daniel Mueller-Gritschneder, Sani R. Nassif, Ulf Schlichtmann, Norbert Wehn
A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience
IEEE Micro 33(4)
July 2013

Xin Pan
On the Sizing of Analog Integrated Circuits towards Lifetime Robustness
PhD Thesis
Technische Universität München
July 2013

Veit B. Kleeberger, Helmut Graeb, Ulf Schlichtmann
Predicting Future Product Performance: Modeling and Evaluation of Standard Cells in FinFET Technologies
In: ACM/IEEE Design Automation Conference (DAC)
June 2013

Georg Georgakos, Ulf Schlichtmann, Reinhard Schneider, Samarjit Chakraborty
Reliability Challenges for Electric Vehicles: From Devices to Architecture and Systems Software
In: ACM/IEEE Design Automation Conference (DAC)
June 2013

Martin Barke, Veit B. Kleeberger, Christoph Werner, Doris Schmitt-Landsiedel, Ulf Schlichtmann
Analysis of Aging Mitigation Techniques for Digital Circuits Considering Recovery Effects
In: edaWorkshop
May 2013

Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann
Post-Route Refinement for High-Frequency PCBs Considering Meander Segment Alleviation (pdf)
In: ACM Great Lake Symposium on VLSI (GLSVLSI)
May 2013

Husni Habal, Helmut Graeb
Evaluating Analog Circuit Performance in Light of MOSFET Aging at Different Time Scales
In: International Conference on IC Design and Technology
May 2013

Michael Eick
Structure and Signal Path Analysis for Analog and Digital Circuits
PhD Thesis
Technische Universität München
May 2013

Carsten Uphoff, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Application of Dempster-Shafer Theory to Task Mapping under Epistemic Uncertainty
2013 IEEE International Systems Conference
April 2013

Amit Verma, Pritpal Multani, Daniel Mueller-Gritschneder, Vladimir Todorov, Ulf Schlichtmann
A Greedy Approach for Latency-bounded Deadlock-free Routing Path Allocation for Application-specific NoCs
In: International Symposium on Networks-on-Chip (NOCS)
April 2013

Bing Li, Ning Chen, Yang Xu, Ulf Schlichtmann
On Timing Model Extraction and Hierarchical Statistical Timing Analysis (pdf)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32(3), 367-380
March 2013

Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann
A Spectral Clustering Approach to Application-Specific Network-on-Chip Synthesis
In: Design, Automation and Test in Europe (DATE)
March 2013

Daniel Mueller-Gritschneder, Kun Lu, Erik Wallander, Marc Greim, Ulf Schlichtmann
A Virtual Prototyping Platform for Real-time Systems with a Case Study for a Two-wheeled Robot
In: Design, Automation and Test in Europe (DATE)
March 2013

Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Analytical Timing Estimation for Temporally Decoupled TLMs Considering Resource Conflicts
In: Design, Automation and Test in Europe (DATE)
March 2013

Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Fast Cache Simulation for Host-Compiled Simulation of Embedded Software
In: Design, Automation and Test in Europe (DATE)
March 2013

André Lange, Roland Jancke, Joachim Haase, Ingolf Lorenz, Ulf Schlichtmann
Probabilistic Standard Cell Modeling Considering Non-Gaussian Parameters and Correlations
In: ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems
March 2013

Andreas Herkersdorf, Michael Engel, Michael Glaß, Jörg Henkel, Veit B. Kleeberger, Michael A. Kochte, Johannes M. Kühn, Sani R. Nassif, Holm Rauchfuss, Wolfgang Rosenstiel, Ulf Schlichtmann, Muhammad Shafique, Mehdi B. Tahoori, Jürgen Teich, Norbert Wehn, Christian Weis, Hans-Joachim Wunderlich
Cross-Layer Dependability Modeling and Abstraction in Systems on Chip
In: Workshop on Silicon Errors in Logic - System Effects (SELSE)
March 2013

Michael Eick, Helmut Graeb
Towards Automatic Structural Analysis of Mixed-Signal Circuits
In: Analog/RF and Mixed-Signal Circuit Systematic Design
Springer, February 2013

Michael Eick, Devanathan Sridharan, Helmut Graeb
Symmetry Computation for Hierarchical Analog Designs
Poster at FAC Workshop 2013
February 2013

Husni Habal
Constraint-Based Layout-Driven Sizing of Analog Circuits
PhD Thesis
Technische Universität München
February 2013

Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Memory Access Reconstruction Based on Memory Allocation Mechanism for Source-Level Simulation of Embedded Software
In: IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC)
January 2013

2012


Michael Pehl, Helmut Graeb
Tolerance Design of Analog Circuits Using a Branch-and-Bound Based Approach
Journal of Circuits, Systems, and Computers
December 2012

Bing Li, Ning Chen, Ulf Schlichtmann
Statistical Timing Analysis for Latch-Controlled Circuits With Reduced Iterations and Graph Transformations (pdf)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31(11), 1670-1683
November 2012

Michael Pehl
Discrete Sizing of Analog Integrated Circuits
PhD Thesis
Technische Universitaet Muenchen
November 2012

Ning Chen, Bing Li, Ulf Schlichtmann
Iterative Timing Analysis Based on Nonlinear and Interdependent Flipflop Modelling (pdf)
IET Circuits, Devices & Systems
October 2012

Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Hierarchical Control Flow Matching for Source-level Simulation of Embedded Software
In: IEEE International Symposium on System-on-Chip
October 2012

Vladimir Todorov, Alberto Ghiribaldi, Helmut Reinig, Davide Bertozzi, Ulf Schlichtmann
Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs
In: International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS)
October 2012

Michael Eick, Helmut Graeb
Automatische Dimensionierung von Analogschaltungen unter Berücksichtigung von Schaltungssysmmetrien
In: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf
September 2012

Michael Zwerger, Helmut Graeb
Verifikation des Power-Down-Modus von analogen Schaltungen
In: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf
September 2012

Michael Eick, Helmut Graeb
A Versatile Structural Analysis Method for Analog, Digital and Mixed-Signal Circuits
In: Int. Conf. Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
September 2012

Michael Zwerger, Helmut Graeb
Short-Circuit-Path and Floating-Node Verification of Analog Circuits in Power-Down Mode
In: Int. Conf. Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
September 2012

Mirco Meiners, Ralf Sommer, Helmut Graeb
Schematic Driven MEMS Design
In: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
September 2012

Christoph Knoth
Accurate Waveform-based Timing Analysis with Systematic Current Source Models
PhD Thesis
Technische Universität München
September 2012

Michael Eick, Helmut Graeb
MARS: Matching-driven Analog Sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
August 2012

Dominik Lorenz, Martin Barke, Ulf Schlichtmann
Efficiently analyzing the impact of aging effects on large integrated circuits
Microelectronics Reliability 52(8), 1546-1552
August 2012

Xin Pan, Helmut Graeb
Reliability Optimization of Analog Integrated Circuits Considering the Trade-off between Lifetime and Area
Microelectronics Reliability 52(8), 1559-1564
August 2012

Alejandro Masrur, Philipp Kindt, Martin Becker, Samarjit Chakraborty, Veit B. Kleeberger, Martin Barke, Ulf Schlichtmann
Schedulability Analysis for Processors with Aging-Aware Autonomic Frequency Scaling
In: International Conference on Embedded and Real-Time Computing Systems and Applications
August 2012

Martin Barke, Michael Kärgel, Weiyun Lu, Felix Salfelder, Lars Hedrich, Markus Olbrich, Martin Radetzki, Ulf Schlichtmann
Robustness Validation of Integrated Circuits and Systems
In: Asia Symposium on Quality Electronic Design (ASQED)
July 2012

Martin Barke, Dominik Lorenz, Ulf Schlichtmann
Robustheitsvalidierung digitaler Schaltungen und Systeme mittels effizienter Alterungsanalyse
In: edaWorkshop
May 2012

Sani R. Nassif, Veit B. Kleeberger, Ulf Schlichtmann
Goldilocks failures: not too soft, not too hard
In: IEEE International Reliability Physics Symposium (IRPS)
April 2012

Dominik Lorenz
Aging Analysis of Digital Integrated Circuits
PhD Thesis
Technische Universität München
April 2012

Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Accurately Timed Transaction Level Models for Virtual Prototyping at High Abstraction Level
In: Design, Automation and Test in Europe (DATE)
March 2012

Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann
Automated Construction of a Cycle-Approximate Transaction Level Model of a Memory Controller
In: Design, Automation and Test in Europe (DATE)
March 2012

Christoph Knoth, Hela Jedda, Ulf Schlichtmann
Current Source Modeling for Power and Timing Analysis at Different Supply Voltages
In: Design, Automation and Test in Europe (DATE)
March 2012

Helmut Graeb
ITRS 2011 Analog EDA Challenges and Approaches
In: Design, Automation and Test in Europe (DATE)
March 2012

Yang Xu, Bing Li, Ralph Hasholzner, Bernhard Rohfleisch, Christian Haubelt, Jürgen Teich
Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis
In: Design, Automation and Test in Europe (DATE)
March 2012

Qingqing Chen, György Csaba, Paolo Lugli, Ulf Schlichtmann, Ulrich Rührmair
Characterization of the Bistable Ring PUF
In: Proceedings of the Design, Automation and Test in Europe Conference (DATE 2012)
March 2012

Christoph Knoth, Ulf Schlichtmann
Characterization of Standard Cells
In: Process Variations and Probabilistic Integrated Circuit Design, Chap. 4.1
Ed.: Manfred Dietrich and Joachim Haase
Springer, 2012

Bing Li, Ulf Schlichtmann
Mathematical Modeling of Process Variations
In: Process Variations and Probabilistic Integrated Circuit Design, Chap. 3.3
Ed.: Manfred Dietrich and Joachim Haase
Springer, 2012

Bing Li, Ulf Schlichtmann
Statistical Static Timing Analysis
In: Process Variations and Probabilistic Integrated Circuit Design, Chap. 4.3
Ed.: Manfred Dietrich and Joachim Haase
Springer, 2012

Helmut Graeb
From Sizing over Design Centering and Pareto Optimization to Tolerance Pareto Optimization of Electronic Circuits
In: Mathematics in Industry 16
Springer, 2012

2011


Veit B. Kleeberger, Sebastian Kiesel, Ulf Schlichtmann, Samarjit Chakraborty
Program-Aware Circuit Level Timing Analysis
In: International Symposium on Integrated Circuits (ISIC)
December 2011

Michael Pehl, Michael Zwerger, Helmut Graeb
Variability-Aware Automated Sizing of Analog Circuits Considering Discrete Design Parameters
In: International Symposium on Integrated Circuits (ISIC)
December 2011

Bing Li, Ning Chen, Ulf Schlichtmann
Fast statistical timing analysis for circuits with Post-Silicon Tunable clock buffers (pdf)
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 2011

Jörg Henkel, Lars Bauer, Joachim Becker, Oliver Bringmann, Uwe Brinkschulte, Samarjit Chakraborty, Michael Engel, Rolf Ernst, Hermann Härtig, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, Wolfgang Rosenstiel, Ulf Schlichtmann, Olaf Spinczyk, Mehdi Tahoori, Jürgen Teich, Norbert Wehn, Hans Joachim Wunderlich
Design and Architectures for Dependable Embedded Systems
In: International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS)
October 2011

Ning Chen, Bing Li, Ulf Schlichtmann
Iterative Timing Analysis Considering Interdependency of Setup and Hold Times
In: International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
September 2011

Ning Chen, Bing Li, Ulf Schlichtmann
Timing Modeling of Flipflops Considering Aging Effects
In: International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
September 2011

Daniel Mueller-Gritschneder, Kun Lu, Ulf Schlichtmann
Control-flow-driven Source Level Timing Annotation for Embedded Software Models on Transaction Level
In: EUROMICRO Conference on Digital System Design (DSD)
September 2011

Christoph Knoth, Carsten Uphoff, Sebastian Kiesel, Ulf Schlichtmann
SWAT: Simulator for Waveform-Accurate Timing including Parameter Variations and Transistor Aging
In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation (PATMOS)
September 2011

Husni Habal, Helmut Graeb
Constraint-Based Layout-Driven Sizing of Analog Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30(8), 1089,1102
August 2011

Veit B. Kleeberger, Ulf Schlichtmann
Zuverlässigkeit digitaler Schaltungen unter Einfluss von intrinsischem Rauschen
Advances in Radio Science 9
August 2011

Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Removal of Unnecessary Context Switches from the SystemC Simulation Kernel for Fast VP Simulation
In: International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)
July 2011

Veit B. Kleeberger, Ulf Schlichtmann
Reliability Analysis of Digital Circuits Considering Intrinsic Noise
In: Asia Symposium on Quality Electronic Design (ASQED)
July 2011

Michael Eick, Helmut Graeb
Unified Generation of Analog Sizing and Placement Constraints
Talk
http://www.async.ece.utah.edu/FAC2011/
July 2011

Qingqing Chen, György Csaba, Paolo Lugli, Ulf Schlichtmann, Ulrich Rührmair
The Bistable Ring PUF: A New Architecture for Strong Physical Unclonable Functions
In: Proceedings of the IEEE Int. Symposium on Hardware-Oriented Security and Trust (HOST 2011), Best Paper Award Nomination
June 2011

Kun Lu, Daniel Mueller-Gritschneder, Wolfgang Ecker, Volkan Esen, Michael Velten, Ulf Schlichtmann
An Approach toward Accurately Timed TLM+ for Embedded System Models
In: edaWorkshop
May 2011

Xin Pan, Helmut Graeb
Reliability Optimization of Analog Circuits with Aged Sizing Rules and Area Trade-off
In: edaWorkshop
May 2011

Martin Strasser
Deterministische hierarchische Platzierung analoger integrierter Schaltungen
PhD Thesis
Technische Universität München
April 2011

Zhonglei Wang, Kun Lu, Andreas Herkersdorf
An Approach to Improve Accuracy of Source-Level TLMs of Embedded Software
In: Design, Automation and Test in Europe (DATE)
March 2011

Aurelien Tchegho
Verfahren zum eingebauten Selbsttest von analogen und gemischt analog-digitalen integrierten Schaltungen
PhD Thesis
Technische Universität München
March 2011

Michael Eick, Martin Strasser, Kun Lu, Ulf Schlichtmann, Helmut Graeb
Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30(2), 180-193
February 2011

Michael Pehl, Helmut Graeb
An SQP and Branch-and-Bound Based Approach for Discrete Sizing of Analog Circuits
In: Advances in Analog Circuits, Chap. 13
Ed.: Esteban Tlelo-Cuautle
InTech, February 2011

Xin Pan, Helmut Graeb
Lifetime Yield Optimization of Analog Circuits Considering Process Variations and Parameter Degradations
In: Advances in Analog Circuits, Chap. 6
Ed.: Esteban Tlelo-Cuautle
InTech, February 2011

Qingqing Chen, György Csaba, Paolo Lugli, Ulf Schlichtmann, Martin Stutzmann, Ulrich Rührmair
Circuit-Based Approaches to SIMPL Systems
Journal of Circuits, Systems, and Computers 20(1), 1-17
January 2011

Helmut Graeb
Analog Layout Synthesis - A Survey of Topological Approaches
Springer, 2011

Martin Strasser, Michael Eick, Helmut Graeb, Ulf Schlichtmann
Deterministic Analog Placement by Enhanced Shape Functions
In: Analog Layout Synthesis
Springer, 2011

2010


Michael Pehl, Michael Zwerger, Helmut Graeb
Sizing Analog Circuits Using an SQP and Branch and Bound Based Approach
In: IEEE International Conference on Electronics, Circuits and Systems (ICECS)
December 2010

Martin Barke, Lars Hedrich, Domenik Helms, Weiyun Lu, Markus Olbrich, Martin Radetzki, Björn Sander, Volker Schöber, Dieter Treytnar
ROBUST: Entwurf Robuster Nanoelektronischer Systeme
newsletter edacentrum
November 2010

Dominik Lorenz, Martin Barke, Ulf Schlichtmann
Aging analysis at gate and macro cell level
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 2010

Bing Li, Ning Chen, Ulf Schlichtmann
Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods (pdf)
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 2010

Xin Pan, Helmut Graeb
Reliability Analysis of Analog Circuits Using Quadratic Lifetime Worst-Case Distance Prediction
In: IEEE Custom Integrated Circuits Conference (CICC)
September 2010

Christoph Knoth, Irina Eichwald, Petra Nordholz, Ulf Schlichtmann
White-Box Current Source Modeling Including Parameter Variation and Its Application in Timing Simulation
In: International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
September 2010

Martin Radetzki, Oliver Bringmann, Wolfgang Nebel, Markus Olbrich, Felix Salfelder, Ulf Schlichtmann
Robustheit nanoelektronischer Schaltungen und Systeme
In: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf
September 2010

Dominik Lorenz, Martin Barke, Ulf Schlichtmann
Timing-Modell für Makrozellen zur Alterungsanalyse
In: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf
September 2010

Helmut Graeb
From Sizing over Design Centering and Pareto Optimization to Tolerance Pareto Optimization of Electronic Circuits
In: Int. Conf. on Scientific Computing in Electrical Engineering (SCEE)
September 2010

Dominik Lorenz, Georg Georgakos, Ulf Schlichtmann
Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level
it - Information Technology 4
August 2010

Bing Li
Hierarchical Statistical Static Timing Analysis Considering Process Variations
PhD Thesis
Technische Universität München
July 2010

Tobias Massier
On the Structural Analysis of CMOS and Bipolar Analog Integrated Circuits
PhD Thesis
Technische Universität München
May 2010

Ulrich Rührmair, Qingqing Chen, Martin Stutzmann, Paolo Lugli, Ulf Schlichtmann, György Csaba
Towards Electrical, Integrated Implementations of SIMPL Systems
In: Information Security Theory and Practice. Security, Privacy and Trust in Computing Systems and Ambient Intelligent Ecosystems. Proceedings of the 4th International Workshop in Information Security Theory and Practices (WISTP 2010)
April 2010

Xin Pan, Helmut Graeb
Lifetime Yield Optimization: Towards a Robust Analog Design for Reliability
In: Design, Automation and Test in Europe (DATE) University Booth
March 2010

Daniel Mueller-Gritschneder, Helmut Graeb
Computation of Yield-optimized Pareto Fronts for Analog Integrated Circuit Specifications
In: Design, Automation and Test in Europe (DATE)
March 2010

Michael Eick, Martin Strasser, Helmut Graeb, Ulf Schlichtmann
Automatic Generation of Hierarchical Placement Rules for Analog Integrated Circuits
In: ACM/SIGDA International Symposium on Physical Design (ISPD)
March 2010

Dominik Lorenz, Martin Barke, Daniel Mueller-Gritschneder, Georg Georgakos, Ulf Schlichtmann
Aging model for timing analysis at register-transfer-level
In: ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems
March 2010

Xin Pan, Helmut Graeb
Reliability Analysis of Analog Circuits by Lifetime Yield Prediction Using Worst-Case Distance Degradation Rate
In: IEEE International Symposium on Quality Electronic Design (ISQED)
March 2010

Daniel Mueller-Gritschneder, Helmut Graeb
Berechnung von ausbeuteoptimierten Spezifikationsparetofronten für analoge integrierte Schaltungen
In: ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG)
March 2010

Michael Pehl, Helmut Graeb
Dimensionierung Analoger Schaltungen mit diskreten Parametern unter Verwendung eines Zufalls- und Gradientenbasierten Ansatzes
In: ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG)
March 2010

Martin Strasser, Michael Eick, Helmut Graeb, Ulf Schlichtmann
Zur effizienten Berücksichtigung von Mindestabständen bei analogen Platzierverfahren
In: ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG)
March 2010

Husni Habal, Helmut Graeb
Accurate Analog Circuit Optimization with Layout Synthesis and Parasitic Extraction
In: Design, Automation and Test in Europe (DATE) University Booth
March 2010

Martin Strasser, Helmut Graeb, Ulf Schlichtmann
Plantage+, Fully Automated, Industrial Level Analog Layout Tool
In: Design, Automation and Test in Europe (DATE) University Booth
March 2010

Gyorgy Csaba, Xueming Ju, Zhiqian Ma, Qingqing Chen, Wolfgang Porod, Jürgen Schmidhuber, Ulf Schlichtmann, Paolo Lugli, Ulrich Rührmair
Application of mismatched cellular nonlinear networks for physical cryptography
In: Proceedings of the 11th IEEE International Workshop on Cellular Nanoscale Networks and their Applications (CNNA 2010)
March 2010

2009


Ning Chen, Bing Li, Ulf Schlichtmann
Sensitivity Based Parameter Reduction for Statistical Analysis of Circuit Performance
In: IEEE International Conference on Electronics, Circuits and Systems (ICECS)
December 2009

Christoph Knoth, Veit B. Kleeberger, Petra Nordholz, Ulf Schlichtmann
Characterization and Implementation of Nonlinear Logic Cell Models for Analog Circuit Simulation
In: International Symposium on Integrated Circuits (ISIC)
December 2009

Michael Pehl, Helmut Graeb
RaGAzi: A Random and Gradient-Based Approach to Analog Sizing for Mixed Discrete and Continuous Parameters
In: International Symposium on Integrated Circuits (ISIC)
December 2009

Xin Pan, Helmut Graeb
Degradation-Aware Analog Design Flow for Lifetime Yield Analysis and Optimization
In: IEEE International Conference on Electronics, Circuits and Systems (ICECS)
December 2009

Qingqing Chen, György Csaba, Xueming Ju, Srinivas Bangalore Natarajan, Paolo Lugli, Martin Stutzmann, Ulf Schlichtmann, Ulrich Rührmair
Analog Circuits for Physical Cryptography
In: Proceedings of the International Symposium on Integrated Circuits (ISIC 2009), Best Paper Award
December 2009

Bing Li, Ning Chen, Ulf Schlichtmann
Timing model extraction for sequential circuits considering process variations (pdf)
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 2009

Helmut Graeb, Xin Pan
Optimierung integrierter Schaltungen im Hinblick auf Alterungseinfluesse
newsletter edacentrum, 11-14
October 2009

Christoph Knoth, Veit B. Kleeberger, Petra Nordholz, Ulf Schlichtmann
Fast and Waveform Independent Characterization of Current Source Models
In: IEEE/VIUF International Workshop on Behavioral Modeling and Simulation (BMAS)
September 2009

Dominik Lorenz, Georg Georgakos, Ulf Schlichtmann
Alterungsanalyse digitaler Schaltungen auf Gatterebene
In: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf
September 2009

Michael Eick, Martin Strasser, Helmut Graeb, Ulf Schlichtmann
Automatische Generierung hierarchischer Platzierungsregeln für analoge integrierte Schaltungen
In: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf
September 2009

Aurelien Tchegho, Sebastian Sattler, Helmut Graeb
Walshfunktionen für das Testen von Mixed-Signal Schaltungen
In: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf
September 2009

Engin Avci, Martin Strasser, Helmut Graeb, Ulf Schlichtmann
A Free-Shape Router for Analog and RF Applications
In: European Conference on Circuit Theory and Design (ECCTD)
August 2009

Daniel Mueller-Gritschneder, Helmut Graeb, Ulf Schlichtmann
A Successive Approach to Compute the Bounded Pareto Front of Practical Multi-objective Optimization Problems
SIAM Journal on optimization 20(2), 915--934
July 2009

Ulrich Rührmair, Qingqing Chen, Paolo Lugli, Ulf Schlichtmann, Martin Stutzmann, György Csaba
Towards Electrical, Integrated Implementations of SIMPL Systems
Cryptology ePrint Archive
June 2009

Dominik Lorenz, Georg Georgakos, Ulf Schlichtmann
Aging Analysis of Circuit Timing Considering NBTI and HCI
In: IEEE International On-Line Testing Symposium (IOLTS)
June 2009

Aurelien Tchegho, Sebastian Sattler, Helmut Graeb
Mixed-signal testing using Walsh functions
In: IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW)
June 2009

Daniel Mueller-Gritschneder
Deterministic Performance Space Exploration of Analog Integrated Circuits Considering Process Variations and Operating Conditions
PhD Thesis
Technische Universität München
June 2009

Jun Zou
Hierarchical Optimization of Large-Scale Analog/Mixed-Signal Circuits Based-on Pareto-Optimal Fronts
PhD Thesis
June 2009

György Csaba, Xueming Ju, Qingqing Chen, Wolfgang Porod, Jürgen Schmidhuber, Ulf Schlichtmann, Paolo Lugli, Ulrich Rührmair
On-Chip Electric Waves: An Analog Circuit Approach to Physical Uncloneable Functions
Cryptology ePrint Archive
May 2009

Christoph Knoth, Veit B. Kleeberger, Ning Chen, Petra Nordholz, Ulf Schlichtmann
Waveform-based Timing Analysis for Digital Circuits using Current Source Models and Model Order Reduction
In: edaWorkshop
May 2009

Ulf Schlichtmann, Manuel Schmidt, Harald Kinzelbach, Michael Pronath, Volker Glöckel, Manfred Dietrich, Uwe Eichler, Joachim Haase
Digital design at a crossroads - How to make statistical design methodologies industrially relevant
In: Design, Automation and Test in Europe (DATE)
April 2009

Bing Li, Ning Chen, Manuel Schmidt, Walter Schneider, Ulf Schlichtmann
On Hierarchical Statistical Static Timing Analysis (pdf)
In: Design, Automation and Test in Europe (DATE)
April 2009

Martin Strasser, Helmut Graeb, Ulf Schlichtmann
Plantage - A Deterministic Analog Placement Approach
In: Design, Automation and Test in Europe (DATE) University Booth
April 2009

Helmut Graeb, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Pareto Optimization of Analog Circuits considering Variability
International Journal of Circuit Theory and Applications 37(2), 283-299
March 2009

Aurelien Tchegho, Heinz Mattes, Sebastian Sattler, Helmut Graeb
Analyse und Untersuchung der Quantisierungseffekte beim Goertzel-Filter
Advances in Radio Science - Kleinheubacher Berichte 7, 73--81
2009

Helmut Graeb, F. Balasa, R. Castro-Lopez, Y.-W. Chang, F. V. Fernandez, P.-H. Lin, Martin Strasser
Analog Layout Synthesis - Recent Advances in Topological Approaches
In: Design, Automation and Test in Europe (DATE)
2009

E. Barke, D. Grabowski, Helmut Graeb, L. Hedrich, St. Heinen, R. Popp, S. Steinhorst, Y. Wang
Formal Approaches to Analog Circuit Verification
In: Design, Automation and Test in Europe (DATE)
2009

2008


Tobias Massier, Helmut Graeb, Ulf Schlichtmann
The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(12), 2209--2222
December 2008

Manuel Schmidt
Waveform Based Statistical Timing Analysis of Integrated Digital Circuits
PhD Thesis
Technische Universität München
December 2008

Martin Strasser, Michael Eick, Helmut Graeb, Ulf Schlichtmann, Frank M. Johannes
Deterministic Analog Circuit Placement using Hierarchically Bounded Enumeration and Enhanced Shape Functions
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 2008

Michael Pehl, Tobias Massier, Helmut Graeb, Ulf Schlichtmann
A Random and Pseudo-Gradient Approach for Analog Circuit Sizing with Non-Uniformly Discretized Parameters
In: IEEE International Conference on Computer Design (ICCD)
October 2008

Christoph Knoth, Veit B. Kleeberger, Manuel Schmidt, Bing Li, Ulf Schlichtmann
Transfer System Models of Logic Gates for Waveform-based Timing Analysis
In: International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)
October 2008

Walter Schneider, Manuel Schmidt, Bing Li, Ulf Schlichtmann
A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA
In: International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
September 2008

Bing Li, Christoph Knoth, Manuel Schmidt, Walter Schneider, Ulf Schlichtmann
Static Timing Model Extraction for Combinational Circuits (pdf)
In: International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
September 2008

Peter Spindler, Ulf Schlichtmann, Frank M. Johannes
Kraftwerk2 -- A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(8), 1398--1411
August 2008

Peter Spindler
Efficient Quadratic Placement of VLSI Circuits
PhD Thesis
Technische Universität München
June 2008

Martin Strasser, Michael Eick, Helmut Graeb, Frank M. Johannes, Ulf Schlichtmann
Ein hierarchisches Platzierungsverfahren für analoge Schaltungen
In: edaWorkshop
May 2008

Manuel Schmidt, Harald Kinzelbach, Ulf Schlichtmann
Genauere Laufzeitanalyse digitaler Schaltungen durch Berücksichtigung statistischer Schwankungen der Signalformen
In: edaWorkshop
May 2008

Peter Spindler, Ulf Schlichtmann, Frank M. Johannes
Abacus: Fast Legalization of Standard Cell Circuits with Minimal Movement
In: ACM/SIGDA International Symposium on Physical Design (ISPD)
April 2008

Christoph Knoth, Daniel Platte, Thomas Halfmann, Jochen Broz, Peter Rotter
Generierung effizienter Verhaltensmodelle mittels Modellkompilierung und Modellreduktion
In: ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG)
April 2008

Helmut Graeb, Daniel Mueller, Ulf Schlichtmann
Pareto-Optimierung analoger Schaltungen mit Parametertoleranzen
In: ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG)
April 2008

Michael Pehl, Tobias Massier, Helmut Graeb, Ulf Schlichtmann
Optimierung analoger Schaltungen mit geordneten diskret veränderlichen Parametern
In: ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG)
April 2008

Tobias Massier, Helmut Graeb, Ulf Schlichtmann
Sizing Rules for Bipolar Analog Circuit Design
In: Design, Automation and Test in Europe (DATE)
March 2008

Manuel Schmidt, Harald Kinzelbach, Ulf Schlichtmann
Variational Waveform Propagation for Accurate Statistical Timing Analysis
In: ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems
February 2008

Aurelien Tchegho, Heinz Mattes, Sebastian Sattler
Optimal high-resolution spectral analyzer
In: Design, Automation and Test in Europe (DATE)
2008

Tobias Massier, Helmut Graeb
Dimensionierungsregeln für analoge Bipolarschaltungen
In: ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG)
2008

Aurelien Tchegho, Heinz Mattes, Sebastian Sattler
Optimaler hochauflösender Spektralanalysator
In: ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG)
2008

Volkan Esen
A New Assertion Language Covering Multiple Levels of Abstraction
PhD Thesis
Technische Universität München
2008

2007


Guido Stehr, Helmut Graeb, Kurt Antreich
Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26(10), 1733--1748
October 2007

Peter Spindler, Frank M. Johannes
Kraftwerk --- A Fast and Robust Quadratic Placer Using an Exact Linear Net Model
In: Modern Circuit Placement --- Best Practices and Results
Springer, September 2007

Jun Zou, Daniel Mueller, Helmut Graeb, Ulf Schlichtmann
Optimization of SC ΣΔ Modulators based on Worst-Case-Aware Pareto-Optimal Fronts
In: IEEE Custom Integrated Circuits Conference (CICC)
September 2007

Manuel Schmidt, Bing Li, Walter Schneider, Harald Kinzelbach, Ulf Schlichtmann
Statistical Timing Analysis using Weibull Waveform Modeling
In: International Symposium on Integrated Circuits (ISIC)
September 2007

Helmut Graeb, Daniel Mueller, Ulf Schlichtmann
Pareto Optimization of Analog Circuits considering Variability
In: European Conference on Circuit Theory and Design (ECCTD)
August 2007

Walter Schneider, Bing Li, Manuel Schmidt, Ulf Schlichtmann
A New Bounding Technique for Handling Arbitrary Correlations in Path-Based Statistical STA
In: edaWorkshop
June 2007

Christoph Grimm, Roland Jahnke, Lars Hedrich, Sorin Huss, Helmut Graeb
Struktursynthese von Analogen und Mixed-Signal Schaltungen: Schwarze Magie?
In: edaWorkshop
June 2007

Peter Spindler, Frank M. Johannes
Fast and Accurate Routing Demand Estimation for Efficient Routability-driven Placement
In: Design, Automation and Test in Europe (DATE)
April 2007

Daniel Mueller, Helmut Graeb, Ulf Schlichtmann
Trade-Off Design of Analog Circuits using Goal Attainment and Wave Front Sequential Quadratic Programming
In: Design, Automation and Test in Europe (DATE)
April 2007

Jun Zou, Daniel Mueller, Helmut Graeb, Ulf Schlichtmann
Pareto-Front Computation and Automatic Sizing of CPPLLs
In: IEEE International Symposium on Quality Electronic Design
March 2007

Walter Schneider, Manuel Schmidt, Ulf Schlichtmann
Statistische Laufzeitmodellierung digitaler Gatter mittels analytischem Timing-Modell und Dichte-Transformationssatz
In: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf
March 2007

Helmut Graeb, Jun Zou, Daniel Mueller, Ulf Schlichtmann
Hierarchische Optimierung einer Phasenregelschaltung
In: ASIM/GI-Fachgruppentagung Simulation technischer Systeme/Grundlagen und Methoden in Modellbildung und Simulation
February 2007

Helmut Graeb
Analog Design Centering and Sizing
Springer, 2007

Ulf Schlichtmann, Helmut Graeb
Integrated circuit design: dealing with variations
In: PAMM Proc. Appl. Math. Mech.
2007

2006


Daniel Mueller, Helmut Graeb, Ulf Schlichtmann
Optimierung analoger Schaltungsbloecke mittels Pareto-Wellenfront-Optimierung
In: ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG)
September 2006

M. Buehler, J. Koehl, J. Bickford, J. Hibbeler, Ulf Schlichtmann, R. Sommer, Michael Pronath, A. Ripp
DFM/DFY Design for Manufacturability and Yield - Influence of Process Variations in Digital, Analog and Mixed-Signal Circuit Design
In: Design, Automation and Test in Europe (DATE)
May 2006

Jun Zou, Daniel Mueller, Helmut Graeb, Ulf Schlichtmann
A CPPLL Hierarchical Optimization Methodology Considering Jitter, Power and Locking Time
In: ACM/IEEE Design Automation Conference (DAC)
2006

Ulf Schlichtmann
Statistical Design for Digital Circuits: Statistical Static Timing Analysis (SSTA)
In: Design, Automation and Test in Europe (DATE)
2006

Daniel Mueller, Guido Stehr, Helmut Graeb, Ulf Schlichtmann
Fast Evaluation of Analog Circuit Structures by Polytopal Approximations
In: IEEE International Symposium on Circuits and Systems (ISCAS)
2006

Peter Spindler, Frank M. Johannes
Fast and Robust Quadratic Placement based on an Accurate Linear Net Model
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
2006

2005


Daniel Mueller, Guido Stehr, Helmut Graeb, Ulf Schlichtmann
Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen
Informatik 2005, Beiträge der 35 Jahrestagung der Gesellschaft für Informatik 1, 334-338
September 2005

Jun Zou, Daniel Mueller, Helmut Graeb, Ulf Schlichtmann, Eckhard Hennig, Ralf Sommer
Fast Automatic Sizing of a Charge Pump Phase-Locked Loop based on Behavioral Models
In: IEEE International Behavioral Modeling and Simulation Conference
September 2005

Daniel Mueller, Guido Stehr, Helmut Graeb, Ulf Schlichtmann
Deterministic Approaches to Analog Performance Space Exploration (PSE)
In: ACM/IEEE Design Automation Conference (DAC)
June 2005

Bernd Obermeier
Mehrzieloptimierung beim Plazieren integrierter Schaltungen
PhD Thesis
Technischne Universität München
March 2005

Bernd Obermeier, Hans Ranke, Frank M. Johannes
Kraftwerk --- A Versatile Placement Approach
In: ACM/SIGDA International Symposium on Physical Design (ISPD)
2005

Alexander Frey, Meinrad Schienle, Christian Paulus, Jun Zou, Franz Hofmann, Petra Schindler-Bauer, Birgit Holzapfl, Melanie Atzesberger, Gottfried Beer, Michaela Fritz, Thomas Haneder, Hans-Christian Hanke, Roland Thewes
A Digital CMOS DNA Chip
In: IEEE International Symposium on Circuits and Systems (ISCAS)
2005

Guido Stehr, Helmut Graeb, Kurt Antreich
Ein linearer Ansatz zur effizienten Abschätzung der Leistungsfähigkeit analoger Schaltungen
In: ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG)
2005

Ulrich Seidl
Layout-basiertes Retiming für FPGAs
PhD Thesis
Technische Universität München
2005

Guido Stehr
On the Performance Space Exploration of Analog Integrated Circuits
PhD Thesis
tum
2005

Michael Pronath
Test Design for Analog Integrated Circuits
PhD Thesis
Technische Universität München
2005

2004


Guido Stehr, Helmut Graeb, Kurt Antreich
Analog Performance Space Exploration by Fourier-Motzkin Elimination with Application to Hierarchical Sizing
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 2004

Ulf Schlichtmann, Helmut Graeb, Ralf Sommer, Eckhard Hennig, Frank Schenkel, Thomas Ifström
Systematic Analog/Mixed-Signal Design -- Yield Optimization of Analog Circuits with WiCkeD
In: MEDEA Forum
November 2004

Ulf Schlichtmann
Design Methodology Innovations Address Manufacturing Technology Challenges: Power and Performance (Invited Paper)
In: EUROMICRO Conference
August 2004

Bernd Obermeier, Frank M. Johannes
Quadratic Placement Using an Improved Timing Model
In: ACM/IEEE Design Automation Conference (DAC)
June 2004

Bernd Obermeier, Frank M. Johannes
Temperature-Aware Global Placement
In: Asia and South Pacific Design Automation Conference
January 2004

Christoph Heer, Ulf Schlichtmann
Ultra Low-Power Design: Device and Logic Design Approaches
In: Ultra Low-Power Electronics and Design
Kluwer Academic Publishers, 2004

Volker Glöckel
Entwurfsverfahren zum impliziten funktionalen Test analoger integrierter Schaltungen
PhD Thesis
Technische Universität München
2004

2003


Tobias Massier, Guido Stehr, Helmut Graeb
Ein Beitrag zur Automatisierung der Strukturanalyse und der impliziten Spezifikation von analogen integrierten Schaltungen
7. GMM/ITG Diskussionssitzung Entwurf von Analogschaltungen (ANALOG '03), 31-36
June 2003

Guido Stehr, Helmut Graeb, Kurt Antreich
Feasibility Regions and their Significance to the Hierarchical Optimization of Analog and Mixed-Signal Systems
International Series of Numerical Mathematics 146, 167--184
2003

Kurt J. Antreich, Helmut Graeb
Circuit Optimization driven by Worst-Case Distances
In: The Best of ICCAD - 20 Years of Excellence in Computer-Aided Design
Kluwer Academic Publishers, 2003

Michael Pronath, Helmut Graeb, Kurt Antreich
On Parametric Test Design for Analog Integrated Circuits considering Error in Measurement and Stimulus
In: Modeling, Simulation and Optimization of Integrated Circuits
Birkhäuser Verlag, 2003

Guido Stehr, Helmut Graeb, Kurt Antreich
Performance Trade-off Analysis of Analog Circuits By Normal-Boundary Intersection
In: ACM/IEEE Design Automation Conference (DAC)
2003

Ulrich Seidl, Klaus Eckl, Frank Johannes
Performance-directed Retiming for FPGAs using Post-placement Delay Information
In: Design, Automation and Test in Europe (DATE)
2003

U. Seidl, K. Eckl, F. Johannes
Layout-basiertes Retiming für FPGAs
In: Entwurf Integrierter Schaltungen (E.I.S.-Workshop)
2003

Guido Stehr, Michael Pronath, Frank Schenkel, Helmut Graeb, Kurt Antreich
Initial Sizing of Analog Integrated Circuits by Centering within Topology-Given Implicit Specifications
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
2003

Guido Stehr, Helmut Graeb, Kurt Antreich
Hierarchische Simulation von Mixed-Signal-Schaltungen
In: Informationstagung Mikroelektronik 2003 (ME '03)
2003

Guido Stehr, Helmut Graeb, Kurt Antreich
Untersuchung der Leistungsfähigkeit analoger Schaltungen mit Hilfe von Dimensionierungsregeln und nichtlinearer Mehrziel-Optimierung
In: ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG)
2003

Klaus Eckl
Technologienahe Retimingverfahren zur Optimierung synchroner digitaler Schaltungen
PhD Thesis
Technische Universität München
2003

Frank Schenkel
Tolerance Analysis and Design Centering of Analog Circuits with Consideration of Mismatch
PhD Thesis
Technische Universität München
2003

Alfred Kölbl
Verifikation digitaler Schaltungen mittels symbolischer Simulation
PhD Thesis
tum
2003

2002


Matthias Senn, Ulrich Seidl, Frank Johannes
High Quality Deterministic Timing Driven FPGA Placement
In: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
February 2002

Alfred Kölbl, James Kukula, Kurt Antreich, Robert Damiano
Handling Special Constructs in Symbolic Simulation
In: ACM/IEEE Design Automation Conference (DAC)
2002

Michael Pronath, Helmut Graeb, Kurt Antreich
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits
In: Design, Automation and Test in Europe (DATE)
2002

R. Schwencker, Frank Schenkel, Michael Pronath, Helmut Graeb
Analog Circuit Sizing using Adaptive Worst-Case Parameter Sets
In: Design, Automation and Test in Europe (DATE)
2002

R. Schwencker, Frank Schenkel, Michael Pronath, Helmut Graeb
Dimensionierung analoger integrierter Schaltungen mittels adaptiver Worst-Case-Parametersätze
In: GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden
2002

Helmut Graeb, S. Zizala, J. Eckmüller, Kurt Antreich
Eine Systematik von Dimensionierungsregeln für den Entwurf analoger integrierter Schaltungen
In: GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden
2002

Michael Pronath, Helmut Graeb, Kurt Antreich
Simulation und Testentwurf für ,,Floating-Gate`` Defekte (FGD) in analogen integrierten Schaltungen
In: GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden
2002

Michael Pronath, Helmut Graeb, Kurt Antreich
Der Einfluss von Ungenauigkeiten im Teststimulus auf den Test analoger Schaltungen
In: ITG/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen
2002

Frank Schenkel, Michael Pronath, Helmut Graeb
WiCkeD 3: Design Centering and Mismatch Analysis for Analog Integrated Circuits
In: Design, Automation and Test in Europe (DATE 02) Designers' Forum
2002

Michael Pronath, Helmut Graeb, Kurt Antreich
Design of Optimal Inplicit Tests for Parametric Faults considering Errors of Test Stimuli and of Measurements
In: IEEE European Test Workshop (ETW)
2002

Ulf Schlichtmann
Systems are made from Transistors: UDSM Technology Creates New Challenges for Library and IC Developement
In: Digital System Design Symposium
2002

Guido Stehr, Helmut Graeb, Kurt Antreich
Dimensionierungsnebenbedingungen bei der hierarchischen Optimierung von Mixed-Signal-Systemen
In: ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG)
2002

Matthias A. Senn
Plazierverfahren für anwenderprogrammierbare Logikbausteine (FPGAs)
PhD Thesis
tum
2002

Norbert Fröhlich
Verfahren zum Schaltungspartitionieren für die parallele Simulation auf Transistorebene
PhD Thesis
tum
2002

Robert Schwencker
Zur Dimensionierung analoger integrierter Schaltungen unter Berücksichtigung struktureller Nebenbedingungen
PhD Thesis
tum
2002

2001


Guido Stehr, Helmut Graeb, Kurt Antreich
A Hierarchical Optimization Approach for Analog and Mixed-Signal Systems
In: Forum on Design Languages (FDL)
September 2001

Matthias Senn, Bernd Obermeier, Frank M. Johannes
Ein Ein-Schritt-Plazierverfahren für FPGAs
In: Entwurf Integrierter Schaltungen (E.I.S.-Workshop)
April 2001

Bernd Obermeier, Frank M. Johannes, V. Meyer zu Bexten
Floorplanning/Plazieren für mixed-signal SoCs
In: Entwurf Integrierter Schaltungen (E.I.S.-Workshop)
April 2001

Volker Glöckel, Michael Pronath, Helmut Graeb
Deterministischer parametrischer Testentwurf für analoge integrierte Schaltungen mit Testbeobachtungen unter Anwendung von Ergebnissen aus dem Toleranzentwurf
In: ITG/GMM/GI Testmethoden und Zuverlässigkeit von Schaltungen und Systemen
February 2001

Frank Schenkel, Michael Pronath, S. Zizala, R. Schwencker, Helmut Graeb, Kurt Antreich
Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search
In: ACM/IEEE Design Automation Conference (DAC)
2001

Alfred Kölbl, James Kukula, Robert Damiano
Symbolic RTL Simulation
In: ACM/IEEE Design Automation Conference (DAC)
2001

Frank Schenkel, Michael Pronath, Helmut Graeb, Kurt Antreich
A Fast Method for Identifying Matching-Relevant Transistor Pairs
In: IEEE Custom Integrated Circuits Conference (CICC)
2001

Matthias Senn, Ulrich Seidl, Frank Johannes
A Two Phase Approach to Timing Driven FPGA Placement
In: IEEE International Conference on Computer Design (ICCD)
2001

Michael Pronath, Helmut Graeb, Kurt Antreich
Estimation of the Influence of Test Stimulus Precision on Test Quality for Parametric Faults in Analog Integrated Circuits
In: IEEE International Workshop on Mixed Signal Testing
2001

Helmut Graeb, S. Zizala, J. Eckmueller, Kurt Antreich
The Sizing Rules Method for Analog Integrated Circuit Design
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
2001

Stephan Zizala
Numerische Verhaltensmodellierung analoger CMOS-Schaltungen unter Berücksichtigung von Dimensionierungsregeln
PhD Thesis
Technische Universität München
2001

Paul Tafertshofer
Test Pattern Generation and Verification for Logic Circuits
PhD Thesis
tum
2001

Paul Tafertshofer
Test Pattern Generation and Verification for Logic Circuits
PhD Thesis
Technische Universität München
2001

2000


Kurt Antreich, J. Eckmüller, Helmut Graeb, Michael Pronath, Frank Schenkel, R. Schwencker, S. Zizala
WiCkeD: Analyse und Dimensionierung analoger Schaltungen unter Berücksichtigung von Mismatch
In: ITG Workshop Mikroelektronik für die Informationstechnik
November 2000

Robert Schwencker, Christian Sporrer, Helmut Graeb
A Method for the Generation of Declarative Models for Interface Circuits
In: Symbolic Methods and Applications in Circuit Design (SMACD)
October 2000

Josef Eckmüller, Roland Jancke, Stephan Zizala, Peter Trappe, Peter Schwarz
Eine Methodik zur Modellierung komplexer Mixed-Signal Baugruppen
In: Abschluss-Workshop des Smart-Systems-Engineering(SSE)-Projekts Verhaltensmodellierung, Mixed-Signal-Modellierung und Simulation (HDL)
October 2000

Paul Tafertshofer, Andreas Ganz, Kurt Antreich
IGRAINE - an Implication GRaph bAsed engINE for fast implication, justification, and propagation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19(8), 907--927
August 2000

Andreas Ganz, Paul Tafertshofer
Parallel Path Classification for Path Delay Fault Testing and Timing Analysis
In: European Conference on Parallel Computing (Euro-Par)
August 2000

Josef Fleischmann
Codesign of Hardware/Software Systems Based on Java
PhD Thesis
tum
July 2000

Kurt Antreich, J. Eckmueller, Helmut Graeb, Michael Pronath, Frank Schenkel, R. Schwencker, S. Zizala
WiCkeD: Analog Circuit Synthesis Incorporating Mismatch
In: IEEE Custom Integrated Circuits Conference (CICC)
May 2000

Guenter Stenz, Bernhard M. Riess, Bernhard Rohfleisch, Frank M. Johannes
Performance Optimization by Interacting Netlist Transformations and Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19(3), 350-358
March 2000

Norbert Fröhlich, Volker Glöckel, Josef Fleischmann
A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level
In: Design, Automation and Test in Europe (DATE)
March 2000

Robert Schwencker, Frank Schenkel, Helmut Graeb, Kurt Antreich
The Generalized Boundary Curve -- A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits
In: Design, Automation and Test in Europe (DATE)
March 2000

Rainer Kress, Klaus Buchenrieder, Josef Fleischmann
Java-basiertes Codesign
Elektronik Praxis, 110-114
February 2000

Kurt Antreich
Ein Puzzle aus 10 Million Teilen
forschung - Das Magazin der Deutschen Forschungsgemeinschft (DFG), 9-11
February 2000

R. Kress, K. Buchenrieder, J. Fleischmann
Codesign of Networked Embedded Systems
In: Embedded Intelligence Conference
February 2000

Michael Pronath, Volker Glöckel, Helmut Graeb, Kurt Antreich
Testentwurf für analoge Komponenten gemischt analog-digitaler Schaltungen basierend auf dem Übertragungsverhalten
In: Architekturentwurf für eingebettete Systeme (AES)
January 2000

Norbert Fröhlich, Volker Glöckel, Georg Denk
A New Multi-Way partitioning Method for Parallel Circuit Simulation
In: SFB 342 Methods and Tools for the Efficient Use of Parallel Systems
TU-München, 2000

Andreas Ganz, Paul Tafertshofer
Parallel Path Classification for Path Delay Fault Testing and Timing Analysis
In: SFB 342 Methods and Tools for the Efficient Use of Parallel Systems
TU-München, 2000

Michael Pronath, Volker Gloeckel, Helmut Graeb
A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
2000

Andreas Ganz
Effiziente Verfahren zu Analyse und Test von Laufzeiteigenschaften integrierter Schaltungen
PhD Thesis
tum
2000

Günter Stenz
Verfahren zur Optimierung von Signallaufzeiten bei der Layoutsynthese integrierter Schaltungen
PhD Thesis
tum
2000

1999


Rolf Schlagenhaft
Dynamischer Lastausgleich verteilter diskreter Simulation
PhD Thesis
tum
December 1999

Paul Tafertshofer, Andreas Ganz
SAT Based ATPG Using Fast Justification and Propagation in the Implication Graph
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 1999

R. Jancke, S. Zizala, J. Eckmüller, P. Trappe
Modellierung komplexer Baugruppen
In: Smart System Engineering -- HDL-VMS-Statusseminar
November 1999

Walter M. Lindermeir, Helmut Graeb, Kurt J. Antreich
Analog Testing by Characteristic Observation Inference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 18(9), 1353-1368
September 1999

Bernd Wurth, Ulf Schlichtmann, Klaus Eckl, Kurt J. Antreich
Functional Multiple-Output Decomposition with Application to Technology Mapping for Lookup Table-Based FPGAs
ACM Transactions on Design Automation of Electronic Systems 4(3), 313-350
July 1999

Klaus Eckl, Jean Christophe Madre, Peter Zepter, Christian Legl
A Practical Approach to Multiple-Class Retiming
In: ACM/IEEE Design Automation Conference (DAC)
June 1999

Josef Fleischmann, Klaus Buchenrieder, Rainer Kress
Java Driven Codesign and Prototyping of Networked Embedded Systems
In: ACM/IEEE Design Automation Conference (DAC)
June 1999

Hans Eisenmann
Ein universelles Plazierverfahren für integrierte Schaltungen
PhD Thesis
tum
June 1999

Paul Tafertshofer, Andreas Ganz
ATPG Using Fast Justification and Propagation on the Implication Graph
In: IEEE European Test Workshop (ETW)
May 1999

Josef Eckmüller, Stephan Zizala, Alexander Schwaferts
Modellierung analoger Schaltungsblöcke
In: Workshop zum Förderschwerpunkt Smart System Engineering
April 1999

Michael Pronath, Volker Glöckel, Helmut Graeb, Kurt Antreich
Simulationsbasierter Testentwurf für gemischt analog-digitale Systeme
it+ti, Informationstechnik und Technische Informatik 41(2), 42--45
March 1999

R. Schwencker, J. Eckmüller, Helmut Graeb, Kurt Antreich
Automating the Sizing of Analog CMOS-Circuits by Consideration of Structural Constraints
In: Design, Automation and Test in Europe (DATE)
March 1999

Josef Fleischmann, Klaus Buchenrieder, Rainer Kress
Codesign of Embedded Systems based on Java and Reconfigurable Hardware Components
In: Design, Automation and Test in Europe (DATE)
March 1999

Klaus Eckl, Christian Legl
Retiming Sequential Circuits with Multiple Register Classes
In: Design, Automation and Test in Europe (DATE)
March 1999

Andreas Ganz, Paul Tafertshofer
An Efficient Framework for Functional Path Analysis
In: ACM/IEEE Int. Workshop on Timing Issues in the Spec. and Syn. of Dig. Systems
March 1999

Josef Fleischmann, Klaus Buchenrieder
Prototyping Networked Embedded Systems
IEEE Computer 32(2), 116-119
February 1999

R. Schwencker, J. Eckmüller, Helmut Graeb, Kurt Antreich
Automatische Nominalpunktdimensionierung analoger CMOS-Schaltungen mit Parameterabständen als Zielgrößen
In: GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden
February 1999

Andreas Ganz, Paul Tafertshofer
Effiziente Verfahren zur funktionalen Pfadanalyse
In: ITG/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen
February 1999

Christian Legl
Logiksynthese für wertetabellenbasierte anwenderprogrammierbare Bausteine
PhD Thesis
tum
February 1999

Aiguo Lu, Guenter Stenz, Hans Eisenmann, Frank M. Johannes
Technology Mapping for Simultaneous Gate and Interconnect Optimisation
IEE Proceedings -- Computers and Digital Techniques 146(1), 21-31
January 1999

Robert Schwencker, Frank Schenkel, Helmut Graeb, Kurt Antreich
Automatische Entwurfszentrierung analoger integrierter Komponenten basierend auf der Verallgemeinerten Grenzkurve von Mehrfach-Robustheits-Maßen
In: Entwurf Integrierter Schaltungen (E.I.S.-Workshop)
1999

C. Sporrer, R. Schwencker, T. Latzel, Helmut Graeb
Generierung und Anwendungen von deklarativen Modellen für Treiberschaltungen
In: GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden
1999

Frank Schenkel, Helmut Graeb, Kurt Antreich
Ausbeuteanalyse unter Berücksichtigung lokaler und globaler Parameterschwankungen
In: GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden
1999

Stephan Zizala, Josef Eckmüller, Helmut Graeb
Effiziente Modellierung integrierter analoger CMOS-Schaltungen durch Berücksichtigung von Struktureigenschaften
In: GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden
1999

Rolf Schlagenhaft
Dynamischer Lastausgleich optimistisch synchronisierter, verteilter Simulation
In: GI-Workshop Verteilte Simulation und parallele Prozesse
1999

1998


Aiguo Lu, Hans Eisenmann, Guenter Stenz, Frank M. Johannes
Combining Technology Mapping with Post-Placement Resynthesis for Performance Optimization
In: IEEE International Conference on Computer Design (ICCD)
October 1998

Robert Schwencker, Helmut Graeb, Thomas Latzel, Christian Sporrer
Interface Circuits and Symbolic Analysis
In: Symbolic Methods and Applications in Circuit Design (SMACD)
October 1998

Martin Klaus Ruhwandl
Simulation von Verbindungsleitungsnetzen in integrierten Schaltungen mit Berücksichtigung der nichtlinearen Eigenschaften des Treibers
PhD Thesis
tum
October 1998

Christian Legl, Bernd Wurth, Klaus Eckl
Computing Support-Minimal Subfunctions During Functional Decomposition
IEEE Transactions on VLSI Systems 6(3), 354--363
September 1998

Stephan Zizala, Josef Eckmueller, Helmut Graeb
Fast Calculation of Analog Circuits' Feasibility Regions by Low Level Functional Measures
In: IEEE Int. Conf. on Electronics, Circuits and Systems
September 1998

Josef Fleischmann, Klaus Buchenrieder, Rainer Kress
Co-Design of Reconfigurable Embedded Systems based on JAVA Specification
In: GI/ITG Workshop Java und eingebettete Systeme
September 1998

Norbert Fröhlich, Bernhard M. Riess, Utz A. Wever, Qinghua Zheng
A New Approach for Parallel Simulation of VLSI Circuits on a Transistor Level
IEEE Transactions on Circuits and Systems CAS 45(6), 601--613
June 1998

Hans Eisenmann, Frank M. Johannes
Generic Global Placement and Floorplanning
In: ACM/IEEE Design Automation Conference (DAC)
June 1998

Gunter Strube
Robuste Verfahren zur Worst-Case- und Ausbeute-Analyse analoger integrierter Schaltungen
PhD Thesis
tum
April 1998

Josef Fleischmann, Klaus Buchenrieder, Rainer Kress
A Hardware/Software Prototyping Environment for Dynamically Reconfigurable Embedded Systems
In: IEEE Int. Workshop on Hardware/Software Codesign
March 1998

Walter M. Lindermeir, Thomas J. Vogels, Helmut Graeb
Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults
In: Design, Automation and Test in Europe (DATE)
February 1998

Josef Eckmueller, Martin Groepl, Helmut Graeb
Hierarchical Characterization of Analog Integrated CMOS Circuits
In: Design, Automation and Test in Europe (DATE)
February 1998

Aiguo Lu, Guenter Stenz, Frank M. Johannes
Technology Mapping for Minimizing Gate and Routing Area
In: Design, Automation and Test in Europe (DATE)
February 1998

Josef Eckmüller
Zur rechnergestützten Dimensionierung analoger integrierter Schaltungen unter besonderer Berücksichtigung von Struktureigenschaften
PhD Thesis
tum
January 1998

Martin Eisele
Einfluß von Parameterschwankungen auf die Ausbeute digitaler Niedervoltschaltungen
PhD Thesis
Technische Universität München
1998

1997


Paul Tafertshofer, Andreas Ganz, Manfred Henftling
A SAT-Based Implication Engine for Efficient ATPG, Equivalence Checking, and Optimization of Netlists
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 1997

Andreas Ganz
Automatic Test Pattern Generation
In: Dynamic Load Distribution for Parallel Applications
Teubner-Texte zur Informatik, September 1997

Rolf Schlagenhaft
MPSIM - Parallel Event Driven Simulation of Logic Circuits by Time Warp
In: Dynamic Load Distribution for Parallel Applications
Teubner Verlag, September 1997

Xiaochun Lin, Erik Dagless, Aiguo Lu
Technology Mapping of LUT based FPGAs for Delay Optimisation
In: International Workshop on Field-Programmable Logic and Applications (FPL)
September 1997

Norbert Fröhlich, Rolf Schlagenhaft, Josef Fleischmann
A New Approach for Partitioning VLSI Circuits on Transistor Level
In: ACM/SCS/IEEE Workshop on Parallel and Distributed Simulation (PADS)
June 1997

Thomas Schnekenburger, Guenter Stenz, Henning Spruth
Problem-Oriented Parallelization of an Iterative Placement Algorithm
In: International Conference on Parallel and Distributed Processing Techniques and Applications
June 1997

Kurt Antreich, Andreas Ganz, Paul Tafertshofer
Statistical Analysis of Delay Faults - Theory and Efficient Computation
Archiv für Elektronik und Übertragungstechnik (AEÜ) 51(3), 117-130
May 1997

Alfred Kölbl, Bernd Wurth
A New Method for the Approximate Computation of Observability Relations
In: International Workshop on Logic Synthesis (IWLS)
May 1997

Paul Tafertshofer, Christian Ebner, Andreas Ganz, Manfred Henftling
A SAT-Based Implication Engine for Efficient Derivation of Indirect Implications
In: International Workshop on Logic Synthesis (IWLS)
May 1997

Klaus Eckl, Christian Legl, Bernd Wurth
An Implicit Approach to Functional Decomposition of Incompletely Specified Boolean Functions
In: International Workshop on Logic Synthesis (IWLS)
May 1997

Christian Legl, Peter Vanbekbergen, Albert Wang
Retiming of Edge-Triggered Circuits with Multiple Clocks and Load Enables
In: International Workshop on Logic Synthesis (IWLS)
May 1997

Andreas Ganz, Paul Tafertshofer, Hannes Wittmann
Statistical Analysis of Delay Faults
In: IEEE European Test Workshop (ETW)
May 1997

Paul Tafertshofer, Massoud Pedram
Factored Edge-Valued Binary Decision Diagrams
Formal Methods in System Design 10(2/3), 243-270
April 1997

Günter Stenz, Berhard M. Riess, Bernhard Rohfleisch, Frank M. Johannes
Timing Driven Placement in Interaction with Netlist Transformations
In: ACM/SIGDA International Symposium on Physical Design (ISPD)
April 1997

Josef Fleischmann, Rolf Schlagenhaft, Martin Peller, Norbert Fröhlich
OLIVIA: Objectoriented Logicsimulation Implementing the VITAL Standard
In: Great Lakes Symposium on VLSI (GLS-VLSI)
March 1997

Walter M. Lindermeir, Thomas Vogels, Helmut Graeb
Erkennung parametrischer Fehler mittels IDD-Messungen in analogen integrierten Schaltungen
In: ITG/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen
March 1997

Josef Fleischmann, Rolf Schlagenhaft, Martin Peller
Objektorientierte Logiksimulation nach dem VITAL Standard
In: ITG/GI/GMM-Workshop Hardwarebeschreibungssprachen und Modellierungsparadigmen
February 1997

Paul Tafertshofer, Andreas Ganz, Manfred Henftling
Reducing the Complexity of Path Classification by Reconvergence Analysis
In: Asia and South Pacific Design Automation Conference
January 1997

Norbert Fröhlich, Rolf Schlagenhaft, Andreas Ganz, Josef Fleischmann
Object Orientation in Time Warp Simulation
In: International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA)
1997

Bernhard Rohfleisch
Optimierung von Netzlisten kombinatorischer Schaltungen
PhD Thesis
tum
1997

Michael Hermann
Technologieabbildung und Testvorbereitung für programmierbare Logikbausteine mit komplexen Grundzellen
PhD Thesis
Technische Universität München
1997

Walter Matthias Lindermeir
Testentwurf für analoge integrierte Schaltungen mit charakteristischen Beobachtungen
PhD Thesis
tum
1997

1996


Walter M. Lindermeir
Design of Robust Test Criteria in Analog Testing
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 1996

Josef Eckmüller, Gunter Strube, Helmut Graeb
Diagnose für integrierte Analogschaltungen
In: GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden
October 1996

W. M. Lindermeir, Helmut Graeb
Entwurf robuster Testkriterien für das Prüfen analoger integrierter Schaltungen
In: GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden
October 1996

Wolfgang Eisenmann, Helmut Graeb
Modellierung der Verlustleistung, der Zuverlässigkeit und der elektromagnetischen Verträglicheit für die Logiksimulation
In: GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden
October 1996

Martin K. Ruhwandl, Helmut Graeb
Schnelle Interconnectsimulation von RLC-Leitungen mit Berücksichtigung von Treibernichtlinearitäten
In: GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden
October 1996

Gunter Strube, Josef Eckmüller, Helmut Graeb
Zuverlässige Empfindlichkeitsberechnung für die Analogoptimierung
In: GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden
October 1996

Helmut Graeb, Guntram Müller-Liebler, Gunter Strube
WiCkeD: Worst-Case- und Ausbeute-Analyse
In: GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden
October 1996

Peter H. Schneider, Matthias A. Senn, Bernd Wurth
Power Analysis for Sequential Circuits at Logic Level
In: European Design Automation Conference with EURO-VHDL (EURO-DAC)
September 1996

Tobias H. Abthoff, Frank M. Johannes
TINA: Analog Placement using Enumerative Techniques Capable of Optimizing both Area and Net Length
In: European Design Automation Conference with EURO-VHDL (EURO-DAC)
September 1996

Christian Legl, Klaus Eckl, Bernd Wurth
Performance-Directed Technology Mapping for LUT-based FPGAs -- What Role Do Decomposition and Covering Play?
In: International Workshop on Field-Programmable Logic and Applications (FPL)
September 1996

Peter H. Schneider, Shankar Krishnamoorthy
Effect of Correlations on Accuracy of Power Analysis - An Experimental Study
In: IEEE/ACM/SIGDA International Symposium on Low Power Electronics and Design
August 1996

M. Eisele, J. Berthold, D. Schmitt-Landsiedel, R. Mahnkopf
The Impact of Intra-Die Device Parameter Variations on Path Delays and on the Design for Yield of Low Voltage Digital Circuits
In: IEEE/ACM/SIGDA International Symposium on Low Power Electronics and Design
August 1996

Christian Legl, Bernd Wurth, Klaus Eckl
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs
In: ACM/IEEE Design Automation Conference (DAC)
June 1996

Frank M. Johannes
Partitioning of VLSI Circuits and Systems
In: ACM/IEEE Design Automation Conference (DAC)
June 1996

Bernhard Rohfleisch, Alfred Kölbl, Bernd Wurth
Reducing Power Dissipation after Technology Mapping by Structural Transformations
In: ACM/IEEE Design Automation Conference (DAC)
June 1996

Walter M. Lindermeir
Auswahl signifikanter Meßgrößen für das Testen analoger Schaltungen
In: GI/GMM/ITG Workshop Methoden und Werkzeuge zum Entwurf von Mikrosystemen
June 1996

W. M. Lindermeir
Feature Extraction for Measurement Selection in Analog Testing
In: IEEE International Workshop on Mixed Signal Testing
May 1996

Christian Legl, Bernd Wurth, Klaus Eckl
An Implicit Algorithm For Support Minimization During Functional Decomposition
In: European Design and Test Conference (EDTC)
March 1996

Martin Eisele, J. Berthold, Doris Schmitt-Landsiedel
Laufzeitschwankungen von digitalen Schaltungen bei niedrigsten Versorgungsspannungen und minimalen Transistordimensionen
In: ITG-Fachtagung Mikroelektronik für die Informationstechnik
March 1996

Paul Tafertshofer, Manfred Henftling, Hannes Wittmann
Ein schnelles Verfahren zur Ermittlung nichtrelevanter Pfade mit Hilfe der Rekonvergenzanalyse
In: ITG/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen
March 1996

Andreas Ganz, Manfred Henftling, Hannes Wittmann
Zur Berechnung von Verzögerungsdefekt-Wahrscheinlichkeiten
In: ITG/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen
March 1996

Tobias Abthoff
Plazieren der Komponenten integrierter Analogschaltungen
1996

Peter H. Schneider, Ulf Schlichtmann, Bernd Wurth
Fast Power Estimation of Large Circuits
IEEE Design and Test 13(1), 70--78
1996

Bernhard M. Riess, Andreas A. Schoene
A New Layout Design System for Multichip Modules
In: High Performance Design Automation for Multi-Chip Modules and Packages
World Scientific, 1996

Peter Schneider
Analyse des Leistungsverbrauchs integrierter Schaltungen auf Logikebene
PhD Thesis
tum
1996

Manfred Henftling
Berechnung von Testvektoren in digitalen Schaltungen auf der Basis von Klauselsystemen
PhD Thesis
Technische Universität München
1996

Bernd Wurth
Logic Synthesis with the Boolean Model
PhD Thesis
Technische Universität München
1996

Bernhard Riess
Physical Design for Multichip Modules
PhD Thesis
tum
1996

Wolfgang Eisenmann
Schnelle Simulation der Verlustleistung und der Zuverlässigkeit von hochintegrierten CMOS-Schaltkreisen auf Gatterebene
PhD Thesis
tum
1996

Hannes Wittmann
Testentwurf zur Erkennung von Verzögerungsfehlern in hochintegrierten Schaltungen
PhD Thesis
tum
1996

1995


M. Eisele, J. Berthold, R. Thewes, E. Wohlrab, D. Schmitt-Landsiedel, W. Weber
Intra-Die Device Parameter Variations and their Impact on Digital CMOS Gates at Low Supply Voltages
In: Int. Electron Devices Meeting
December 1995

Bernhard M. Riess, Hans Eisenmann
Ein Bewertungsverfahren für Plazieralgorithmen
In: Entwurf Integrierter Schaltungen (E.I.S.-Workshop)
November 1995

Manfred Henftling, Hannes C. Wittmann, Kurt J. Antreich
A Single-Path-Oriented Fault-Effect Propagation in Digital Circuits Considering Multiple-Path Sensitization
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 1995

Walter M. Lindermeir, Helmut Graeb, Kurt J. Antreich
Design Based Analog Testing by Characteristic Observation Inference
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 1995

M. Eisele, J. Berthold
Dynamic Gate Delay Modeling for Accurate Estimation of Glitch Power at Logic Level
In: International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
October 1995

Peter H. Schneider
PAPSAS: A Fast Switching Activity Simulator
In: International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
October 1995

Manfred Henftling, Hannes Wittmann, Kurt J. Antreich
A Formal Non-Heuristic ATPG Approach
In: European Design Automation Conference with EURO-VHDL (EURO-DAC)
September 1995

Hannes Wittmann, Manfred Henftling
Path Delay ATPG for Standard Scan Designs
In: European Design Automation Conference with EURO-VHDL (EURO-DAC)
September 1995

Bernhard M. Riess, Heiko A. Giselbrecht, Bernd Wurth
A New K-Way Partitioning Approach for Multiple Types of FPGAs
In: Asia and South Pacific Design Automation Conference
August 1995

Markus Waidelich, Reiner Lederle
A Development System for Fuzzy Hardware
In: European Congress on Intelligent Techniques and Soft Computing (EUFIT)
August 1995

Reiner Lederle, Peter Eubert, Herbert Eichfeld
Hardware Architecture for Fuzzy Control of Electric Feed Drive using a Fuzzy Coprocessor and a Transputernetwork
In: European Congress on Intelligent Techniques and Soft Computing (EUFIT)
August 1995

T. Abthoff, Frank M. Johannes
Analogue Placement using Guided Enumeration
International Journal of Circuit Theory and Applications 23(4), 453-473
July 1995

Bernd Wurth, Klaus Eckl, Kurt Antreich
Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm
In: ACM/IEEE Design Automation Conference (DAC)
June 1995

Bernhard Rohfleisch, Bernd Wurth, Kurt Antreich
Logic Clause Analysis for Delay Optimization
In: ACM/IEEE Design Automation Conference (DAC)
June 1995

Josef Fleischmann, Philip A. Wilsey
Comparative Analysis of Periodic State Saving Techniques in Time Warp Simulators
In: ACM/SCS/IEEE Workshop on Parallel and Distributed Simulation (PADS)
June 1995

Rolf Schlagenhaft, Martin K. Ruhwandl, Christian Sporrer, Herbert Bauer
Dynamic Load Balancing of a Multi-Cluster Simulator on a Network of Workstations
In: ACM/SCS/IEEE Workshop on Parallel and Distributed Simulation (PADS)
June 1995

Bernhard M. Riess, Heiko A. Giselbrecht, Bernd Wurth
K-Way Partitioning for Multiple Type FPGAs
In: GI/ITG Workshop Anwenderprogrammierbare Schaltungen
June 1995

Walter M. Lindermeir, Helmut Graeb, Kurt J. Antreich
Analog Testing by Equivalent-Performance Matching
In: IEEE International Workshop on Mixed Signal Testing
June 1995

Reiner Lederle, Markus Waidelich
Fuzzy Logic Entwicklungssystem für den Fuzzy Logic Coprozessor SAE 81C99
In: VDE/ITG Diskussionssitzung NULLMikroelektronik der Fuzzy-SystemeNULL
June 1995

Bernhard Rohfleisch, Bernd Wurth, Kurt J. Antreich
Delay Optimization of Combinational Circuits by Logic Clause Analysis
In: International Workshop on Logic Synthesis (IWLS)
May 1995

Bernd Wurth, Klaus Eckl, Kurt Antreich
Functional Multiple-Output Decomposition for Lookup-Table Based FPGAs
In: International Workshop on Logic Synthesis (IWLS)
May 1995

Peter H. Schneider, Bernd Wurth
Transition Probability Estimation for Combinational and Sequential Circuits
In: International Workshop on Logic Synthesis (IWLS)
May 1995

Bernhard M. Riess, Gisela Ettelt
SPEED: Fast and Efficient Timing Driven Placement
In: IEEE International Symposium on Circuits and Systems (ISCAS)
April 1995

Walter W. Lindermeir, Helmut Graeb
On the Production Test of Analog Circuits by Statistical Fault Modeling
Archiv für Elektronik und Übertragungstechnik (AEÜ) 49(2), 64--71
March 1995

T. Abthoff, Frank M. Johannes
PLACEBO: Analog Placement with efficient Symmetry Support
Archiv für Elektronik und Übertragungstechnik (AEÜ) 49(2), 55-63
March 1995

Bernd Wurth, Karl Fuchs
A BIST Approach to Delay Fault Testing with Reduced Test Length
In: European Design and Test Conference (EDTC)
March 1995

Bernhard M. Riess, Andreas A. Schoene
Architecture Driven K-Way Partitioning for Multichip Modules
In: European Design and Test Conference (EDTC)
March 1995

Manfred Henftling, Hannes Wittmann
Bit Parallel Test Pattern Generation for Path Delay Faults
In: European Design and Test Conference (EDTC)
March 1995

Hannes Wittmann
Fehlersimulation für Pfadverzögerungsfehler in digitalen Schaltungen mit Standard--Prüfpfad
In: ITG/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen
February 1995

Manfred Henftling
Petri-Netze zur Testmustergenerierung für verschiedene Fehlermodelle
In: ITG/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen
February 1995

Manfred Henftling, Hannes Wittmann
A New Data Structure to Solve the Satisfiability Problem in Digital Circuits
Archiv für Elektronik und Übertragungstechnik (AEÜ) 49(1), 29--36
January 1995

Michael Hermann, Bernhard Rohfleisch, Ulf Schlichtmann, Bernd Wurth
Logic Synthesis for Library-Based Field Programmable Gate Arrays
Archiv für Elektronik und Übertragungstechnik (AEÜ) 49(1), 18--28
January 1995

Peter A. Krauss
Parallelisierung der automatischen Testmustergenerierung in sequentiellen Schaltungen
PhD Thesis
tum
January 1995

Bernhard M. Riess, Andreas A. Schoene
A New Layout Design System for Multichip Modules
International Journal of High Speed Electronics and Systems 6(3), 509-538
1995

Bernd Wurth, Norbert Wehn
Multiple-level logic optimization with Boolean relations
In: Novel Approaches in Logic and Architecture Synthesis
Chapman & Hall, London, 1995

Henning Spruth
Parallele Verfahren zur automatischen Layoutsynthese integrierter Schaltungen
PhD Thesis
tum
1995

1994


Peter A. Krauss, Manfred Henftling
Efficient Fault Ordering for Automatic Test Pattern Generation for Sequential Circuits
In: IEEE Asian Test Symposium (ATS)
November 1994

M. Miura-Mattausch, U. Feldmann, A. Rahm, M. Bollu, D. Savignac
Unified Complete MOSFET Model for Analysis of Digital and Analog Circuits
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 1994

Wolfgang T. Eisenmann, Helmut Graeb
Fast Transient Power and Noise Estimation for VLSI Circuits
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 1994

Konrad Doll, Frank M. Johannes, Kurt J. Antreich
Iterative Placement Improvement by Network Flow Methods
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13(10), 1189-1200
October 1994

W. M. Lindermeir, M. K. Ruhwandl, F. Lenke
Dimensionierung von balancierten Taktbäumen/Teil 1
designelektronik 20(20), 66-68
October 1994

W. M. Lindermeir, M. K. Ruhwandl, F. Lenke
Dimensionierung von balancierten Taktbäumen/Teil 2
designelektronik 21(21), 88-93
October 1994

Reiner E. Lederle, Peter Eubert, Herbert Eichfeld
Fuzzy Logic Control of Electric Feed Drive of CNC Machine Tools
In: European Congress on Intelligent Techniques and Soft Computing (EUFIT)
September 1994

Peter H. Schneider, Ulf Schlichtmann, Kurt J. Antreich
A New Power Estimation Technique with Application to Decomposition of Boolean Functions for Low Power
In: European Design Automation Conference with EURO-VHDL (EURO-DAC)
September 1994

Gunter Strube, Helmut Graeb
ASIS: Automatische Simulator-Steuerung
In: GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden
September 1994

Martin Eisele, Klaus Hentschel, Thomas Künemund
Hardware Realization of Fast Defuzzification by Adaptive Integration
In: IEEE International Conference on Microelectronics for Neural Networks and Fuzzy Systems
September 1994

Michael Hermann, Wolfgang Hoffmann
Fault Modeling and Test Generation for FPGAs
In: International Workshop on Field-Programmable Logic and Applications (FPL)
September 1994

Bernhard M. Riess, Konrad Doll, Frank M. Johannes
Partitioning Very Large Circuits Using Analytical Placement Techniques
In: ACM/IEEE Design Automation Conference (DAC)
June 1994

Manfred Henftling, Hannes C. Wittmann, Kurt J. Antreich
Path Hashing to Accelerate Delay Fault Simulation
In: ACM/IEEE Design Automation Conference (DAC)
June 1994

M. Miura-Mattausch, A. Rahm, M. Bollu, U. Feldmann, D. Savignac
A Novel Consistent MOSFET Model for CAD Application with Reduced Calculation Time
In: IEEE International Symposium on Circuits and Systems (ISCAS)
May 1994

Henning Spruth, Frank M. Johannes, Kurt J. Antreich
PHIroute: A Parallel Hierarchical Sea-of-Gates Router
In: IEEE International Symposium on Circuits and Systems (ISCAS)
May 1994

Peter H. Schneider, Ulf Schlichtmann
Synthese zur Minimierung des Leistungsverbrauchs von FPGAs
In: ITG/GME/GI-Fachtagung Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme
May 1994

Peter A. Krauss
A Distributed Automatic Test Pattern Generation System
In: Lecture Notes in Computer Science No.~796: High--Performance Computing and Networking
Springer--Verlag, April 1994

Peter H. Schneider, Ulf Schlichtmann
Decomposition of Boolean Function for Low Power Based on a New Power Estimation Technique
In: ACM/IEEE International Workshop on Low Power Design
April 1994

Henning Spruth, Frank M. Johannes
Parallel Routing of VLSI Circuits Based on Net Independency
In: IEEE International Parallel Processing Symposium (IPPS)
April 1994

Hannes Wittmann, Manfred Henftling
Efficient Path Identification for Delay Testing --- Time and Space Optimization
In: European Design and Test Conference (EDTC)
February 1994

Bernd Wurth, Norbert Wehn
Efficient calculation of Boolean relations for multi-level logic optimization
In: European Design and Test Conference (EDTC)
February 1994

Bernhard Rohfleisch, Franc Brglez
Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping
In: European Design and Test Conference (EDTC)
February 1994

Kurt Antreich, Helmut Graeb, C. Wieser
Circuit analysis and optimization driven by worst-case distances
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13(1), 57-71
January 1994

Kurt J. Antreich, Michael Hermann, Frank Dresig
Geteilte Logiksynthese für FPGAs
designelektronik 25/26, 74-75
1994

Kurt J. Antreich, Helmut Graeb, Rudolf K. Koblitz
Advanced Yield Optimization Techniques
Elsevier Science Publishers, 1994

Konrad Doll
Ein iteratives Verfahren zum Plazieren von Zellen bei der Layoutsynthese integrierter Schaltungen
PhD Thesis
tum
1994

Ulf Schlichtmann
Logiksynthese für komplexe anwenderprogrammierbare elektronische Bausteine
PhD Thesis
Technische Universität München
1994

Claudia Wieser
Schaltkreisanalyse mit Worst-Case Abständen
PhD Thesis
tum
1994

Christian Sporrer
Verfahren zur Schaltungspartitionierung für die parallele Logiksimulation
PhD Thesis
tum
1994

Herbert Bauer
Verteilte diskrete Simulation komplexer Systeme
PhD Thesis
regent
1994

1993


Bernd Wurth, Norbert Wehn
Multi-Level Logic Optimization with Boolean Relations
In: IFIP Workshop on Logic and Architecture Synthesis
December 1993

Ulf Schlichtmann
Disjunkte Dekomposition Boolescher Funktionen: Eine Neue Betrachtungsweise
In: Entwurf Integrierter Schaltungen (E.I.S.-Workshop)
November 1993

Peter A. Krauss, Kurt J. Antreich
Application of Fault Parallelism to the Automatic Test Pattern Generation for Sequential Circuits
In: Lecture Notes in Computer Science No.~732: Parallel Computer Architectures: Theory, Hardware, Software, Applications
Springer--Verlag, August 1993

Ulf Schlichtmann, Franc Brglez
Efficient Boolean Matching in Technology Mapping with Very Large Cell Libraries
In: IEEE Custom Integrated Circuits Conference (CICC)
May 1993

Ulf Schlichtmann, Franc Brglez, Peter Schneider
Efficient Boolean Matching Based on Unique Variable Ordering
In: International Workshop on Logic Synthesis (IWLS)
May 1993

Karl Fuchs, Hannes C. Wittmann, Kurt J. Antreich
Fast Test Pattern Generation for all Path Delay Faults Considering Various Test Classes
In: European Test Conference (ETC)
April 1993

Karl Fuchs, Hannes C. Wittmann, Konrad Huber
Zur Synthese dynamisch testbarer kombinatorischer Schaltungen
In: ITG/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen
March 1993

Michael Hermann, Ulf Schlichtmann, Kurt J. Antreich
Fast Technology Mapping for Multiplexor-based Architectures with Area/Delay Tradeoff
In: European Conference on Design Automation (EDAC)
February 1993

Hannes C. Wittmann, Bernhard H. Seiß, Kurt J. Antreich
Using Circuit Hierarchy for Fault Simulation in Combinational and Sequential Circuits
In: European Conference on Design Automation (EDAC)
February 1993

Ch. Kredler, Ch. Zillober, Frank M. Johannes, G. Sigl
An application of preconditioned conjugate gradients to relative placement in chip design
International Journal for Numerical Methods in Engineering, 255-271
1993

Kurt Antreich, Helmut Graeb, C. Wieser
Practical methods for worst-case and yield analysis of analog integrated circuits
International Journal of High Speed Electronics and Systems, 261-282
1993

Helmut Graeb, C. Wieser
Methoden zum Toleranzentwurf, Teil 1
designelektronik 10, 30-34
1993

Henning Spruth, Frank M. Johannes
Architectures for Parallel Slicing Enumeration in VLSI Layout
In: Lecture Notes in Computer Science No.~732: Parallel Computer Architectures: Theory, Hardware, Software, Applications
Springer Verlag, 1993

Helmut Graeb, C. Wieser, Kurt Antreich
Improved methods for worst-case analysis and optimization incorporating operating tolerances
In: ACM/IEEE Design Automation Conference (DAC)
1993

Christian Sporrer, Herbert Bauer
Corolla Partitioning for Distributed Logic Simulation of VLSI-Circuits
In: ACM/SCS/IEEE Workshop on Parallel and Distributed Simulation (PADS)
1993

C. Wieser, Helmut Graeb
Verbesserte Methoden zum Toleranzentwurf analoger integrierter Schaltungen
In: GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden
1993

Herbert Bauer, Christian Sporrer
Reducing Rollback Overhead in Time-Warp Based Distributed Simulation with Optimized Incremental State Saving
In: SCS/IEEE Annual Simulation Symposium (ASS)
1993

Bernhard M. Rieß, Konrad Doll, Frank M. Johannes
Partitionierung hochkomplexer Schaltungen unter Nutzung von Plazierungsinformation
In: 6. E.I.S.-Workshop
1993

Karl-Heinz Erhard
Flächenminimierung von Stromversorgungsnetzen für hochintegrierte Schaltungen
PhD Thesis
Technische Universität München
1993

Helmut Graeb
Schaltkreisoptimierung mit Worst-Case-Abständen als Zielgrößen
PhD Thesis
Technische Universität München
1993

Ralf Hartmann
Synthese von DSP-Algorithmen für flexible Multiprozessorstrukturen
PhD Thesis
tum
1993

Matthias Utesch
Zur graphenbasierten hierarchie-erhaltenden Adaptierung des Maskenlayouts integrierter Schaltungen
PhD Thesis
Technische Universität München
1993

1992


Franz Fink, Karl Fuchs, Michael H. Schulz
Robust and Nonrobust Path Delay Fault Simulation by Parallel Processing of Patterns
IEEE Transactions on Computers 41(12), 1527--1536
December 1992

Bernhard H. Seiß, Hannes C. Wittmann
Highly Efficient Fault Simultation Exploiting Hierarchy in Circuit Description
In: IEEE Asian Test Symposium (ATS)
November 1992

Michael Hermann, Ulf Schlichtmann
Schnelle Logiksynthese für FPGAs mit Optimierung des Zeitverhaltens
In: ITG/GME/GI-Fachtagung Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme
November 1992

Hannes C. Wittmann, Bernhard H. Seiß
Hierarchische Fehlersimulation in kombinatorischen Schaltungen
In: ITG/GME/GI--Fachtagung Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme
November 1992

Henning Spruth, Georg Sigl
Parallel Algorithms for Slicing Based Final Placement
In: European Design Automation Conference with EURO-VHDL (EURO-DAC)
September 1992

Ulf Schlichtmann, Franc Brglez, Michael Hermann
Characterization of Boolean Functions for Rapid Matching in EPGA Technology Mapping
In: ACM/IEEE Design Automation Conference (DAC)
June 1992

Elisabeth Auth, Johannes Kastner
ESSENTIAL: Ein automatisches Testmustergenerierungsystem für synchrone Schaltwerke
In: ITG/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen
March 1992

Hannes C. Wittmann
Algorithmen zur schnellen Testmustergenerierung und Fehlersimulation für Verzögerungsfehler
In: GMD/Ariadne-Workshop
March 1992

M. Rösch, Kurt Antreich
Fast steady-state simulation of nonlinear circuits in the frequency domain
Archiv für Elektronik und Übertragungstechnik (AEÜ) 46(3), 168-176
1992

K.-H. Erhard, Frank M. Johannes
Power/ground networks in VLSI: Are general graphs better than trees?
INTEGRATION - the VLSI journal, 91-109
1992

Helmut Graeb, R. Lederle
Circuit yield optimization by analyzing performance statistics
Microprocessing and Microprogramming, 697-704
1992

Herbert Bauer, Christian Sporrer
Distributed Logic Simulation and an Approach to Asynchronous GVT-Calculation
In: ACM/SCS/IEEE Workshop on Parallel and Distributed Simulation (PADS)
1992

Helmut Graeb, C. Wieser, Kurt Antreich
Design verification considering manufacturing tolerances by using worst-case distances
In: European Design Automation Conference with EURO-VHDL (EURO-DAC)
1992

K.-H. Erhard, Frank M. Johannes, R. Dachauer
Topology optimization techniques for power/ground networks in VLSI
In: European Design Automation Conference with EURO-VHDL (EURO-DAC)
1992

Konrad Doll, Frank M. Johannes, Georg Sigl
Accurate Net Models for Placement Improvement by Network Flow Methods
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
1992

Veronika Eisele, Doris Schmitt-Landsiedel
Makromodellierung des Lesevorgangs für die Architekturoptimierung schneller Halbleiterspeicher
In: ITG-Fachtagung Mikroelektronik für die Informationstechnik
1992

Helmut Graeb, C. Wieser
Erweiterte Schaltkreisanalyse mit Worst-Case-Abständen
In: ITG/GME/GI-Fachtagung Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme
1992

Christian Sporrer, Herbert Bauer
Partitioning VLSI-Circuits for Distributed Logic Simulation
In: SCS European Simulation Multiconference (ESM)
1992

Peter A. Krauss
Fehlerparallelisierung bei der automatischen Testmustergenerierung für sequentielle Schaltungen
In: ITG/GME/GI--Fachtagung Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme
1992

Konrad Doll, Frank M. Johannes, Georg Sigl
Placement Improvement by Network Flow Methods
In: Proceedings International Workshop on Layout Synthesis MCNC 1990
1992

Elisabeth Auth
Automatische Testmustergenerierung in synchronen sequentiellen Schaltungen
PhD Thesis
Technische Universität München
1992

Stefan Mayrhofer
Ein laufzeitgesteuertes Plazierungsverfahren für den zellbasierten Layoutentwurf integrierter Schaltungen
PhD Thesis
Technische Universität München
1992

Georg Sigl
Plazierung der Zellen bei der Layoutsynthese mittels Partitionierung und quadratischer Optimierung
PhD Thesis
Technische Universität München
1992

G. Sigl
Plazierung der Zellen bei der Layoutsynthese mittels Partitionierung und quadratischer Optimierung
PhD Thesis
regent
1992

Dieter Pellkofer
Schnelle Fehlersimulation in digitalen Schaltungen
PhD Thesis
regent
1992

Markus Rösch
Schnelle Simulation des stationären Verhaltens nichtlinearer Schaltungen
PhD Thesis
Technische Universität München
1992

Bernhard Seiß
Testpunkteinbau und hierarchische Fehlersimulation in kombinatorischen Schaltungen
PhD Thesis
Technische Universität München
1992

Veronika Eisele
Zur Entwurfsoptimierung statischer Halbleiterspeicher
PhD Thesis
Technische Universität München
1992

Edgar Auer
Zur automatischen Layoutsynthese von Logikzellen
PhD Thesis
Technische Universität München
1992

1991


Karl Fuchs, Franz Fink, Michael H. Schulz
DYNAMITE: An Efficient Automatic Test Pattern Generation System for Path Delay Faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10(10), 1323--1335
October 1991

Herbert Bauer, Christian Sporrer, Hans Thomas Krodel
On Distributed Logic Simulation Using Time Warp
In: IFIP International Conference on Very Large Scale Integration (VLSI)
August 1991

Elisabeth Auth, Michael H. Schulz
A Test--Pattern Generation Algorithm for Sequential Circuits
IEEE Design and Test, 72--86
June 1991

Konrad Doll, Frank M. Johannes, Georg Sigl
Probabilistisches Plazieren von Standardzellen: Eine effiziente Alternative zu Simulated Annealing
In: Entwurf Integrierter Schaltungen (E.I.S.-Workshop)
April 1991

Franz Fink, Karl Fuchs, Michael H. Schulz
An Efficient Parallel Pattern Gate Delay Fault Simulator with Accelerated Detected Fault Size Determination Capabilities
In: European Test Conference (ETC)
April 1991

Bernhard H. Seiß, Pieter M. Trouborst, Michael H. Schulz
Test Point Insertion for Scan--Based BIST
In: European Test Conference (ETC)
April 1991

Jürgen M. Kleinhans, Georg Sigl, Frank M. Johannes, Kurt J. Antreich
GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10(3), 356-365
March 1991

Kurt J. Antreich, Karl Fuchs, Franz Fink
Testen von Laufzeitfehlern in digitalen Schaltungen
Mikroelektronik me 5(4), 170-172
1991

Hartmut Grabinski
Theorie und Simulation von Leitbahnen
Springer-Verlag, 1991

Georg Sigl, Konrad Doll, Frank M. Johannes
Analytical Placement: A Linear or a Quadratic Objective Function?
In: ACM/IEEE Design Automation Conference (DAC)
1991

Kurt Antreich, Helmut Graeb
A unified approach towards nominal and tolerance design
In: World Congress on Computation and Applied Mathematics (IMACS)
1991

V. Eisele, D. Schmitt-Landsiedel
Optimization and Architectural Evaluation of Regular Combinatoric Structures
In: EUROMICRO Conference
1991

Georg Sigl, Ulf Schlichtmann
Goal Oriented Slicing Enumeration through Shape Function Clipping
In: European Conference on Design Automation (EDAC)
1991

Kurt Antreich, Helmut Graeb
Circuit optimization driven by worst-case distances
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
1991

K.-H. Erhard, Frank M. Johannes
Area Minimization of IC power/ground nets by topology optimization
In: IFIP International Conference on Very Large Scale Integration (VLSI)
1991

Konrad Doll, Frank M. Johannes, Georg Sigl
DOMINO: Deterministic Placement Improvement with Hill-Climbing Capabilities
In: IFIP International Conference on Very Large Scale Integration (VLSI)
1991

Karl Fuchs
Testmustergenerierung zur Erkennung von Laufzeitfehlern in hochintegrierten Schaltungen
PhD Thesis
regent
1991

Franz Fink
Zur Simulation von Laufzeitfehlern in hochintegrierten Schaltungen
PhD Thesis
regent
1991

1990


Bernhard H. Seiß, Michael H. Schulz
Ein neues, effizientes Verfahren zum Testpunkteinbau in kombinatorischen Schaltungen
In: Proceedings der GME/GI/ITG--Fachtagung
October 1990

Kurt J. Antreich, Karl Fuchs, Franz Fink
Zum dynamischen Testen kombinatorischer Schaltungen
Frequenz, Fachverlag Schiele & Schön, 103--111
April 1990

K. J. Antreich, H. T. Krodel
Verfahren zur Logiksimulation und Laufzeitmodellierung in digitalen Schaltungen
Archiv für Elektronik und Übertragungstechnik (AEÜ) 44(2), 104-113
1990

W. L. Schiele, A. Schwaferts, K. M. Just, E. Auer
Ein Layoutgenerator für Logikblöcke in SCVS-Schaltungstechnik
Archiv für Elektronik und Übertragungstechnik (AEÜ) 44
1990

Michael H. Schulz, H.-J. Wunderlich
Methoden der Testvorbereitung zum IC-Entwurf
Mikroelektronik me 4(3), 112-115
1990

Kurt Antreich
A case history of cooperation in design automation research
Siemens Review R&D Special, 8-11
1990

K. M. Just, E. Auer, W. L. Schiele, A. Schwaferts
Palace: A layout generator for SCVS logic blocks
In: ACM/IEEE Design Automation Conference (DAC)
1990

H. T. Krodel, K. J. Antreich
An Accurate Model for Ambiguity Delay Simulation
In: European Conference on Design Automation (EDAC)
1990

V. Eisele, B. Hoppe, O. Kiehl
Transmission Gate Delay Models for Circuit Optimization
In: European Conference on Design Automation (EDAC)
1990

Kurt J. Antreich, Dieter Pellkofer
Fast Fault Simulation for VLSI--Logic (invited paper)
In: XXIII General Assembly Of The International Union Of Radio Science (URSI) VLSI--CAD--Session
1990

1989


Thomas M. Sarfert, Remo G. Markgraf, Erwin Trischler, Michael H. Schulz
Hierarchical Test Pattern Generation Based on High--Level Primitives
In: IEEE International Test Conference (ITC)
August 1989

H. Ch. Ranke, Frank M. Johannes
Macrocell Placement by Global Optimization with Uniform Cell Distribution
In: IFIP International Conference on Very Large Scale Integration (VLSI)
August 1989

Michael H. Schulz, Elisabeth Auth
Improved Deterministic Test Pattern Generation with Applications to Redundancy Identification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 8(7), 811--816
July 1989

Michael H. Schulz, Franz Fink, Karl Fuchs
Parallel Pattern Fault Simulation of Path Delay Faults
In: ACM/IEEE Design Automation Conference (DAC)
June 1989

Michael H. Schulz, Elisabeth Auth
ESSENTIAL: An Efficient Self--Learning Test Pattern Generation Algorithm for Sequential Circuits
12th Annual IEEE Workshop on Design for Testability
April 1989

Michael H. Schulz, Dieter Pellkofer
A Three--Valued Fast Fault Simulator for Scan--Based VLSI--Logic
In: European Test Conference (ETC)
April 1989

Michael H. Schulz, Bernhard H. Seiß, Franc Brglez
Hierarchical Fault Simulation in Combinational Circuits
In: European Test Conference (ETC)
April 1989

Kurt Antreich, K. Zibert
Entwurfstechnik für integrierte Schaltungen
Mikroelektronik me 3, 262
1989

D. A. Mlynski, Frank M. Johannes, U. Ph. Lauther, W. Schiele, C. Federschmidt, W. Fleig, H. Vollmer
Physikalischer Entwurf von integrierten Schaltungen
Mikroelektronik me, 264-269
1989

F. Pörnbacher
CANDI: Ein Programmsystem zur Unterstützung des Entwurfs integrierter Schaltungen
ntzArchiv 11, 137-151
1989

F. Pörnbacher
A new method supporting the nominal design of analog integrated circuits with regard to constraints
In: European Conference on Circuit Theory and Design (ECCTD)
1989

B. Hoppe, O. Kiehl, T. Huber, D. Schmitt-Landsiedel, G. Neuendorf, V. Eisele
Polynomial delay models for optimization - based transistor sizing in digital CMOS VLSI circuits
In: European Conference on Circuit Theory and Design (ECCTD)
1989

J. M. Kleinhans, G. Sigl, Frank M. Johannes
Sea-of-Gates Placement by Simultaneous Quadratic Programming Combined with Improved Partitioning
In: IFIP International Conference on Very Large Scale Integration (VLSI)
1989

Hans--Joachim Wunderlich, Michael H. Schulz
Methoden der Testvorbereitung
In: ITG-Fachtagung Mikroelektronik für die Informationstechnik
1989

Frank M. Johannes
Layout-Entwurf
In: Tagungsband ITG-Fachtagung für die Informationstechnik
1989

J. M. Kleinhans
Ein Plazierungsverfahren für den zellenbasierten Layoutentwurf hochintegrierter Schaltungen
PhD Thesis
regent
1989

Hans Thomas Krodel
Verfahren zur Logiksimulation komplexer digitaler Schaltungen mit flexibler Modellierung
PhD Thesis
regent
1989

Fritz Pörnbacher
Zur interaktiven Dimensionierung analoger integrierter Schaltungen unter Berücksichtigung von Nebenbedingungen
PhD Thesis
Technische Universität München
1989

1988


Jürgen M. Kleinhans, Georg Sigl, Frank M. Johannes
GORDIAN: A New Global Optimization / Rectangle Dissection Method for Cell Placement
In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
November 1988

Michael H. Schulz, Elisabeth Auth
Advanced Automatic Test Pattern Generation and Redundancy Identification Techniques
In: IEEE International Symposium on Fault-Tolerant Computing (FTCS)
June 1988

Kurt J. Antreich, Jürgen M. Kleinhans, Karl Fuchs
Zwei- und dreilagiges Channel-Routing mit optimierter Zyklenbehandlung und Pfadverkürzung
Archiv für Elektronik und Übertragungstechnik (AEÜ) 42(1), 9-20
January 1988

Michael H. Schulz, Erwin Trischler, Thomas M. Sarfert
SOCRATES: A Highly Efficient Automatic Test Pattern Generation System
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 7(1), 126--137
January 1988

A. Schütz
Modulgeneratoren vereinfachen ASIC-Design
Elektronik el, 131-134
1988

Kurt Antreich, P. Leibner, F. Pörnbacher
Nominal design of integrated circuits on circuit level by an interactive improvement method
IEEE Transactions on Circuits and Systems CAS 35, 1501-1511
1988

Bernd Schürmann
Hierarchisches Top Down Chip Planning
infospektrum, 57-70
1988

Michael H. Schulz
Testmustergenerierung und Fehlersimulation in digitalen Schaltungen mit hoher Komplexität
PhD Thesis
Technische Universität München
1988

Erwin Trischler
Zur Modellierung digitaler Schaltungen mit AND/OR--Graphen für die automatische Testmustergenerierung
PhD Thesis
Technische Universität München
1988

1987


Michael H. Schulz, Erwin Trischler, Thomas M. Sarfert
SOCRATES: A Highly Efficient Automatic Test Pattern Generation System
In: IEEE International Test Conference (ITC)
September 1987

Kurt J. Antreich, Michael H. Schulz
Fast Fault Simulation for Scan--Based VLSI--Logic
In: Proceedings of the European Conference on Circuit Theory and Design 1987
September 1987

Michael H. Schulz, Franc Brglez
Accelerated Transition Fault Simulation
In: ACM/IEEE Design Automation Conference (DAC)
June 1987

F. Pörnbacher
Switch-Level-Simulation nach dem CSA-Verfahren
ntzArchiv, 231-236
1987

J. M. Kleinhans
Channel-Routing für zwei und drei Verdrahtungsebenen mit Behandlung zyklischer Konflikte
In: Entwurf Integrierter Schaltungen (E.I.S.-Workshop)
1987

J. M. Kleinhans
Efficient algorithms for two- and three-layer channel routing
In: IEEE Proceedings VLSI and Computers, International Conference on Computer Technology, Systems and
1987

Knut M. Just
Zur automatischen Plazierung der Module bei der Layout-Synthese
PhD Thesis
Technische Universität München
1987

Guntram Müller-Liebler
Zur stochastischen Optimierung beim Entwurf integrierter Schaltungen
PhD Thesis
Technische Universität München
1987

1986


Kurt J. Antreich, Michael H. Schulz
Zur schnellen Fehlersimulation in kombinatorischen Schaltungen
Archiv für Elektronik und Übertragungstechnik (AEÜ), 355--361
June 1986

K. M. Just
Zur Plazierung von Standardzellen durch Lösen des Relativplazierungs- und Transportproblems
In: Entwurf Integrierter Schaltungen (E.I.S.-Workshop)
March 1986

P. Leibner
On an Interactive Optimization Method for the Design of Integrated Circuits (in German)
Archiv für Elektronik und Übertragungstechnik (AEÜ) 40, 1-9
1986

Knut M. Just, Jürgen M. Kleinhans, Frank M. Johannes
On The Relative Placement And The Transportation Problem For Standard-Cell Layout
In: ACM/IEEE Design Automation Conference (DAC)
1986

P. Leibner
Rechnerunterstützte Dimensionierung integrierter Schaltungen mittels eines interaktiven Optimierungsverfahrens
In: Entwurf Integrierter Schaltungen (E.I.S.-Workshop)
1986

Peter Leibner
Ein interaktives Optimierungsverfahren zur rechnergestützten Dimensionierung integrierter Schaltungen
PhD Thesis
Technische Universität München
1986

1985


Knut M. Just, Jürgen M. Kleinhans
Zur simultanen Plazierung von Moduln integrierter Schaltungen
Archiv für Elektronik und Übertragungstechnik (AEÜ) 39(4), 217-224
July 1985

Erwin Trischler, Michael H. Schulz
Applications of Testability Analysis to ATG: Methods and Experimental Results
In: IEEE International Symposium on Circuits and Systems (ISCAS)
June 1985

1984


Kurt Antreich, S. Huss
An Interactive Optimization Technique for the Nominal Design of Integrated Circuits
IEEE Transactions on Circuits and Systems CAS 31, 203-212
1984

Fritz Kirsch
Rechnergestützte Lösungsverfahren zur Relativplazierung bei der Layoutsynthese
PhD Thesis
Technische Universität München
1984

1983


Kurt Antreich, J. Armaos
A general approach to statistical circuit design
In: European Conference on Circuit Theory and Design (ECCTD)
1983

Kurt Antreich, P. Leibner
Nominal Design of Integrated Circuits by Interactive Optimization
In: IEEE International Symposium on Circuits and Systems (ISCAS)
1983

Frank M. Johannes, Knut M. Just, Kurt J. Antreich
On the Force Placement of Logic Arrays
In: Proceedings European Conference on Circuit Theory and Design (ECCTD)
1983

1982


Kurt J. Antreich, Frank M. Johannes, Fritz H. Kirsch
Zur Plazierung von Bauelementen
Archiv für Elektronik und Übertragungstechnik (AEÜ) 36(1), 1-8
January 1982

Kurt Antreich, S. Huss
An Interactive Approach to the Optimization of Integrated Circuits (in German)
Archiv für Elektronik und Übertragungstechnik (AEÜ) 36, 327-336
1982

Fritz H. Kirsch
Ein Lösungsverfahren zur Plazierung von Bauelementen mittels eines Kräftemodells
Archiv für Elektronik und Übertragungstechnik (AEÜ) 36(10), 393-401
1982

Kurt Antreich, R. Koblitz
Design Centering by Yield Prediction
IEEE Transactions on Circuits and Systems CAS 29, 88-95
1982

Kurt J. Antreich, Frank M. Johannes, Fritz H. Kirsch
A New Approach for Solving the Placement Problem Using Force Models
In: IEEE International Symposium on Circuits and Systems (ISCAS)
1982

R. Koblitz
Interactive Design Centering by an Efficient Assessment Criterion
In: IEEE International Symposium on Circuits and Systems (ISCAS)
1982

R. Koblitz
Ein Verfahren zur Entwurfszentrierung elektrischer Schaltungen.
PhD Thesis
tum
1982

J. Armaos
Zur Optimierung der Fertigungsausbeute elektrischer Schaltungen unter Berücksichtigung der Parametertoleranzen
PhD Thesis
tum
1982

S. Huss
Zur interaktiven Optimierung integrierter Schaltungen
PhD Thesis
tum
1982

1981


J. Armaos
A general statistical approach to design centering and tolerancing (in German)
Archiv für Elektronik und Übertragungstechnik (AEÜ) 35, 173-178
1981

Kurt Antreich, R. Koblitz
An interactive procedure to design centering
In: IEEE International Symposium on Circuits and Systems (ISCAS)
1981

Waldemar Hauck
Zum rechnergestützten Entwurf quasilinearer Systeme
PhD Thesis
Technische Universität München
1981

1980


R. Koblitz
Design centering and tolerance assignment of electrical circuits with Gaussian-distributed parameter values (in German)
Archiv für Elektronik und Übertragungstechnik (AEÜ) 34, 30-37
1980

Kurt Antreich, G. Müller
On the Interactive Optimization of Electrical Networks (in German)
Archiv für Elektronik und Übertragungstechnik (AEÜ) 34, 89-96
1980

Kurt Antreich, R. Koblitz
A new approach to design centering based on a multiparameter yield-prediction formula
In: IEEE International Symposium on Circuits and Systems (ISCAS)
1980

1979


G. Müller
Interaktive Schaltungsoptimierung und rechnergestützter Abgleich
PhD Thesis
tum
1979

1978


Kurt Antreich, R. Koblitz
Zur Vereinheitlichung der Toleranz- und Empfindlichkeitsanalyse elektrischer Netzwerke
Archiv für Elektronik und Übertragungstechnik (AEÜ) 32, 369-373
1978

1976


G. Müller
On Computer-Aided Tuning of Microwave Filters
In: IEEE International Symposium on Circuits and Systems (ISCAS)
1976