VHDL System Design Laboratory (Praktikum Systementwurf mit VHDL)

Vortragende/r (Mitwirkende/r)
Nummer0000001853
ArtPraktikum
Umfang4 SWS
SemesterWintersemester 2018/19
UnterrichtsspracheEnglisch
Stellung in StudienplänenSiehe TUMonline

Termine

Teilnahmekriterien & Anmeldung

Lernziele

At the end of the module students will be able to analyze and evaluate System-on-Chip and embedded system concepts. They are capable of designing and creating SoCs and embedded systems with their complex system components.

Beschreibung

Concept of System-on-Chip (SoC); build an example of an embedded system with microcontroller, bus and peripherals; first implement an encryption algorithm using a standard hardware description language; then wrap the security module as a peripheral attached to bus; design an interface between peripheral and bus; apply an FPGA design flow for embedded systems, and embedded software for testing the encryption algorithm.

Inhaltliche Voraussetzungen

Fundamentals of digital logic design; Fundamentals of programming

Lehr- und Lernmethoden

Learning method: In addition to the individual methods of the students consolidated knowledge is acquired by providing subtasks of increasing complexity and difficulty in the laboratory notes. Teaching method: Students are free to work on their own, according to their own schedule, on the laboratory tasks. Students can work on the laboratory either in institute rooms, or at home. An adviser is available who will support them in case of significant difficulties. The following kinds of media are used: * Introductory lectures * Lecture slides available * Laboratory notes with detailed descriptions of tasks and tool environments * Individual discussions with advisor

Studien-, Prüfungsleistung

Examination with the following elements: * Written examination 60 min. (40%) * project (60%) Knowledge-based teaching targets are examined with a written examination. Capabilities of designing a System on Chip are examined by a project consisting of design tasks on the System components and the system composition using a hardware description language. The examination is in form of software code and of a documentation of the design.

Empfohlene Literatur

The following literature is recommended: * ANSI, IEEE Standards Board, IEEE Standard VHDL Language Reference Manual: IEEE Std 1076-1993 , New York, 1988, ISBN 1559373768 * Peter J. Ashenden, Designer’s Guide to Vhdl, Morgan Kaufmann Publishers, 1995, ISBN 1558602704 * More literature listed in laboratory notes

Links