Timing of Digital Circuits

Vortragende/r (Mitwirkende/r)
Nummer0000002539
Art
Umfang3 SWS
SemesterWintersemester 2018/19
UnterrichtsspracheEnglisch
Stellung in StudienplänenSiehe TUMonline

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Teilnahmekriterien & Anmeldung

Lernziele

After finishing this course, students can state the concept of digital circuits. They can name the basic techniques used to improve timing performance of such circuits and tell the reasons of adopting such a design style in industry. Students can also relate the theoretical concepts of timing constraints and analysis algorithms with practical circuits and summarize the necessity of such constraints. By applying the discussed techniques to practical examples, students examine their differences so that they can choose and integrate suitable methods to solve problems in real designs. The advanced research topics let them expand the scope of understanding and inspect the limitations of the traditional design concept. They can thus predict and propose advanced methods in designing high-performance low-power circuits in industry.

Beschreibung

The following topics are covered in the lectures: - Challenges and motivations in the development of digital circuits; race condition and hazard in combinational circuits. - Concept of flipflop-based pipeline design and setup/hold time constraints; clock period and frequency; gate library and static timing analysis. - Techniques to improve timing performance, including pipeline, retiming etc. - Aspects of digital design, including clock network, skews, synchronization across different clock domains etc. - Advanced research on timing analysis: process variations and statistical timing analysis (SSTA). The tutorials and the lab cover the following topics: - Introduction of the implementation of VHDL description by the synthesis tool; guidelines of VHDL description. - Pipeline and retiming of digital circuits in VHDL. - Synthesis practice using an FPGA environment. - Implementation of a static timer using C/C++. - Clock skew optimization.

Inhaltliche Voraussetzungen

- Basic knowledge of VHDL and C/C++.

Lehr- und Lernmethoden

The course is partitioned into a teaching part and a self-studying part (the associated lab). The teaching part includes lectures and tutorials. In the lectures, basic concepts of digital circuits are discussed. Visual aids such as PowerPoint slides, overhead projections and handwriting on black board are used. In each lecture, some problems in circuit design are explained first. Then discussions are held to predict possible solutions. Thereafter, academic and industrial techniques are shown and evaluated together with the students. In the tutorials, the techniques introduced in lectures are demonstrated using real examples. Students then practice with small examples and thus get familiar with the design/programming environment. In the associated lab, tasks of implementation of timing algorithms are assigned. Students works individually in finishing these tasks. To achieve this goal, they also need to consult further documents such as scientific papers. Support will be given by the lecturer and teaching assistant regularly and on-demand. Additional electronic media are also used to provide information and support.

Studien-, Prüfungsleistung

The exam is in written form and lasts 60 minutes. The exam includes questions about the concepts discussed in lectures and tutorials. In addition, problems to test the understanding of the course contents and the ability to apply them in practice are included. These problems cover extensive timing-related topics of digital circuits described by, e.g., netlist or HDL.

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