Testing Digital Circuits (Testen digitaler Schaltungen)

Vortragende/r (Mitwirkende/r)
Umfang3 SWS
SemesterWintersemester 2018/19
Stellung in StudienplänenSiehe TUMonline


Teilnahmekriterien & Anmeldung


The manufacturing process of integrated circuits introduces a large variety of physical defects. In order to prevent the delivery of failing silicon devices to the customer, the correct function of delivered integrated circuits has to be guaranteed by testing all devices after they have been fabricated. Testing integrated circuits is one of the core competencies of a semiconductor company. It represents a significant factor in costs and quality. Therefore, testing is considered as an outstanding part of the entire design and manufacturing process of ICs. Furthermore, testing is a domain-crossing topic: The test engineer within a semiconductor company requires a broad expertise covering circuit and system design, circuit simulation and design verification, and physical design. One of the main challenges in testing is costs which have drastically increased over the past years. The access to circuit internal transistors and nodes has to be accomplished by a limited number of external pins. This is increasingly difficult due to the continuous shrinking of device structures. This lecture conveys: * The basic idea of testing. * Relevant failure mechanisms of integrated circuits and the common fault models. * The complexity problem of testing and its resulting limitations. * Methods for test pattern generation (e.g. fault simulation and automatic test generation). * Fundamental measures for designing integrated circuits in order to raise their testability (Design-for-Testability). * Techniques for insertion of built-in self-test (BIST) in integrated circuits. * Techniques for memory testing.