Publikationen
2012
| S. R. Nassif and V. B. Kleeberger and U. Schlichtmann Goldilocks failures: not too soft, not too hard IEEE International Reliability Physics Symposium (IRPS) April 2012 |
| Q. Chen and G. Csaba and P. Lugli and U. Schlichtmann and U. Rührmair Characterization of the Bistable Ring PUF Design, Automation and Test in Europe (DATE) March 2012 |
| K. Lu and D. Mueller-Gritschneder and U. Schlichtmann Accurately Timed Transaction Level Models for Virtual Prototyping at High Abstraction Level Design, Automation and Test in Europe (DATE) March 2012 |
| H. Graeb ITRS 2011 Analog EDA Challenges and Approaches Design, Automation and Test in Europe (DATE) March 2012 |
| Y. Xu and B. Li and R. Hasholzner and B. Rohfleisch and C. Haubelt and J. Teich Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis Design, Automation and Test in Europe (DATE) March 2012 |
| D. Lorenz and M. Barke and U. Schlichtmann Efficiently analyzing the impact of aging effects on large integrated circuits Microelectronics Reliability Microelectronics Reliability February 2012 |
| C. Knoth and H. Jedda and U. Schlichtmann Current Source Modeling for Power and Timing Analysis at Different Supply Voltages Design, Automation and Test in Europe (DATE) 2012 |
| B. Li and U. Schlichtmann Mathematical Modeling of Process Variations Process Variations and Probabilistic Integrated Circuit Design, Springer 2012 |
| B. Li and U. Schlichtmann Statistical Static Timing Analysis Process Variations and Probabilistic Integrated Circuit Design, Springer 2012 |
| C. Knoth and U. Schlichtmann Characterization of Standard Cells Process Variations and Probabilistic Integrated Circuit Design, Springer 2012 |
2011
| V. B. Kleeberger and S. Kiesel and U. Schlichtmann and S. Chakraborty Program-Aware Circuit Level Timing Analysis International Symposium on Integrated Circuits (ISIC) December 2011 |
| M. Pehl and M. Zwerger and H. Graeb Variability-Aware Automated Sizing of Analog Circuits Considering Discrete Design Parameters International Symposium on Integrated Circuits (ISIC) December 2011 |
| B. Li and N. Chen and U. Schlichtmann Fast Statistical Timing Analysis for Circuits with Post-Silicon Tunable Clock Buffers IEEE/ACM International Conference on Computer-Aided Design (ICCAD) November 2011 |
| J. Henkel and L. Bauer and J. Becker and O. Bringmann and U. Brinkschulte and S. Chakraborty and M. Engel and R. Ernst and H. Härtig and L. Hedrich and A. Herkersdorf and R. Kapitza and D. Lohmann and P. Marwedel and M. Platzner and W. Rosenstiel and U. Schlichtmann and O. Spinczyk and M. Tahoori and J. Teich and N. Wehn and H. J. Wunderlich Design and Architectures for Dependable Embedded Systems International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS) October 2011 |
| D. Mueller-Gritschneder and K. Lu and U. Schlichtmann Control-flow-driven Source Level Timing Annotation for Embedded Software Models on Transaction Level EUROMICRO Conference on Digital System Design (DSD) September 2011 |
| C. Knoth and C. Uphoff and S. Kiesel and U. Schlichtmann SWAT: Simulator for Waveform-Accurate Timing including Parameter Variations and Transistor Aging Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation (PATMOS) September 2011 |
| N. Chen and B. Li and U. Schlichtmann Timing Modeling of Flipflops Considering Aging Effects International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) September 2011 |
| N. Chen and B. Li and U. Schlichtmann Iterative Timing Analysis Considering Interdependency of Setup and Hold Times International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) September 2011 |
| H. Habal and H. Graeb Constraint-Based Layout-Driven Sizing of Analog Circuits IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems August 2011 |
| V. B. Kleeberger and U. Schlichtmann Reliability Analysis of Digital Circuits Considering Intrinsic Noise Asia Symposium on Quality Electronic Design (ASQED) July 2011 |
| M. Eick and H. Graeb Unified Generation of Analog Sizing and Placement Constraints Frontiers in Analog Circuit (FAC) Synthesis and Verification July 2011 |
| K. Lu and D. Mueller-Gritschneder and U. Schlichtmann Removal of Unnecessary Context Switches from the SystemC Simulation Kernel for Fast VP Simulation International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) July 2011 |
| Q. Chen and G. Csaba and P. Lugli and U. Schlichtmann and U. Rührmair The Bistable Ring PUF: A New Architecture for Strong Physical Unclonable Functions IEEE Int. Symposium on Hardware-Oriented Security and Trust June 2011 |
| K. Lu and D. Mueller-Gritschneder and W. Ecker and V. Esen and M. Velten and U. Schlichtmann An Approach toward Accurately Timed TLM+ for Embedded System Models edaWorkshop May 2011 |
| X. Pan and H. Graeb Reliability Optimization of Analog Circuits with Aged Sizing Rules and Area Trade-off edaWorkshop May 2011 |
| M. Strasser Deterministische hierarchische Platzierung analoger integrierter Schaltungen PhD Thesis April 2011 |
| A. Tchegho Verfahren zum eingebauten Selbsttest von analogen und gemischt analog-digitalen integrierten Schaltungen PhD Thesis March 2011 |
| Z. Wang and K. Lu and A. Herkersdorf An Approach to Improve Accuracy of Source-Level TLMs of Embedded Software Design, Automation and Test in Europe (DATE) March 2011 |
| X. Pan and H. Graeb Lifetime Yield Optimization of Analog Circuits Considering Process Variations and Parameter Degradations Advances in Analog Circuits, InTech February 2011 |
| M. Pehl and H. Graeb An SQP and Branch-and-Bound Based Approach for Discrete Sizing of Analog Circuits Advances in Analog Circuits, InTech February 2011 |
| M. Eick and M. Strasser and K. Lu and U. Schlichtmann and H. Graeb Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems February 2011 |
| Q. Chen and G. Csaba and P. Lugli and U. Schlichtmann and M. Stutzmann and U. Rührmair Circuit-Based Approaches to SIMPL Systems Journal of Circuits, Systems, and Computers January 2011 |
| H. Graeb Analog Layout Synthesis - A Survey of Topological Approaches Springer 2011 |
| M. Strasser and M. Eick and H. Graeb and U. Schlichtmann Deterministic Analog Placement by Enhanced Shape Functions Analog Layout Synthesis, Springer 2011 |
| M. Strasser and M. Eick and H. Graeb and U. Schlichtmann Deterministic Analog Placement by Enhanced Shape Functions Analog Layout Synthesis, Springer 2011 |
| V. B. Kleeberger and U. Schlichtmann Zuverlässigkeit digitaler Schaltungen unter Einfluss von intrinsischem Rauschen Advances in Radio Science 2011 |
2010
| M. Pehl and M. Zwerger and H. Graeb Sizing Analog Circuits Using an SQP and Branch and Bound Based Approach IEEE International Conference on Electronics, Circuits and Systems (ICECS) December 2010 |
| D. Lorenz and M. Barke and U. Schlichtmann Aging analysis at gate and macro cell level IEEE/ACM International Conference on Computer-Aided Design (ICCAD) November 2010 |
| B. Li and N. Chen and U. Schlichtmann Fast Statistical Timing Analysis of Latch-Controlled Circuits for Arbitrary Clock Periods IEEE/ACM International Conference on Computer-Aided Design (ICCAD) November 2010 |
| M. Barke and L. Hedrich and D. Helms and W. Lu and M. Olbrich and M. Radetzki and B. Sander and V. Schöber and D. Treytnar ROBUST: Entwurf Robuster Nanoelektronischer Systeme newsletter edacentrum November 2010 |
| D. Lorenz and M. Barke and U. Schlichtmann Timing-Modell für Makrozellen zur Alterungsanalyse GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf September 2010 |
| M. Radetzki and O. Bringmann and W. Nebel and M. Olbrich and F. Salfelder and U. Schlichtmann Robustheit nanoelektronischer Schaltungen und Systeme GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf September 2010 |
| X. Pan and H. Graeb Reliability Analysis of Analog Circuits Using Quadratic Lifetime Worst-Case Distance Prediction IEEE Custom Integrated Circuits Conference (CICC) September 2010 |
| H. Graeb From Sizing over Design Centering and Pareto Optimization to Tolerance Pareto Optimization of Electronic Circuits Int. Conf. on Scientific Computing in Electrical Engineering (SCEE) September 2010 |
| C. Knoth and I. Eichwald and P. Nordholz and U. Schlichtmann White-Box Current Source Modeling Including Parameter Variation and Its Application in Timing Simulation International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) September 2010 |
| D. Lorenz and G. Georgakos and U. Schlichtmann Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level it - Information Technology August 2010 |
| B. Li Hierarchical Statistical Static Timing Analysis Considering Process Variations PhD Thesis July 2010 |
| T. Massier On the Structural Analysis of CMOS and Bipolar Analog Integrated Circuits PhD Thesis May 2010 |
| U. Rührmair and Q. Chen and M. Stutzmann and P. Lugli and U. Schlichtmann and G. Csaba Towards Electrical, Integrated Implementations of SIMPL Systems Workshop in Information Security Theory and Practices (WISTP) April 2010 |
| D. Lorenz and M. Barke and D. Mueller-Gritschneder and G. Georgakos and U. Schlichtmann Aging model for timing analysis at register-transfer-level ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems March 2010 |
| M. Eick and M. Strasser and H. Graeb and U. Schlichtmann Automatic Generation of Hierarchical Placement Rules for Analog Integrated Circuits ACM/SIGDA International Symposium on Physical Design (ISPD) March 2010 |
| D. Mueller-Gritschneder and H. Graeb Computation of Yield-optimized Pareto Fronts for Analog Integrated Circuit Specifications Design, Automation and Test in Europe (DATE) March 2010 |
| X. Pan and H. Graeb Lifetime Yield Optimization: Towards a Robust Analog Design for Reliability Design, Automation and Test in Europe (DATE) University Booth March 2010 |
| M. Strasser and H. Graeb and U. Schlichtmann Plantage+, Fully Automated, Industrial Level Analog Layout Tool Design, Automation and Test in Europe (DATE) University Booth March 2010 |
| H. Habal and H. Graeb Accurate Analog Circuit Optimization with Layout Synthesis and Parasitic Extraction Design, Automation and Test in Europe (DATE) University Booth March 2010 |
| X. Pan and H. Graeb Reliability Analysis of Analog Circuits by Lifetime Yield Prediction Using Worst-Case Distance Degradation Rate IEEE International Symposium on Quality Electronic Design (ISQED) March 2010 |
| G. Csaba and X. Ju and Z. Ma and Q. Chen and W. Porod and J. Schmidhuber and U. Schlichtmann and P. Lugli and U. Rührmair Application of mismatched cellular nonlinear networks for physical cryptography IEEE International Workshop on Cellular Nanoscale Networks and their Applications March 2010 |
| M. Pehl and H. Graeb Dimensionierung Analoger Schaltungen mit diskreten Parametern unter Verwendung eines Zufalls- und Gradientenbasierten Ansatzes ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG) March 2010 |
| D. Mueller-Gritschneder and H. Graeb Berechnung von ausbeuteoptimierten Spezifikationsparetofronten für analoge integrierte Schaltungen ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG) March 2010 |
| M. Strasser and M. Eick and H. Graeb and U. Schlichtmann Zur effizienten Berücksichtigung von Mindestabständen bei analogen Platzierverfahren ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG) March 2010 |
2009
| X. Pan and H. Graeb Degradation-Aware Analog Design Flow for Lifetime Yield Analysis and Optimization IEEE International Conference on Electronics, Circuits and Systems (ICECS) December 2009 |
| N. Chen and B. Li and U. Schlichtmann Sensitivity Based Parameter Reduction for Statistical Analysis of Circuit Performance IEEE International Conference on Electronics, Circuits and Systems (ICECS) December 2009 |
| C. Knoth and V. B. Kleeberger and P. Nordholz and U. Schlichtmann Characterization and Implementation of Nonlinear Logic Cell Models for Analog Circuit Simulation International Symposium on Integrated Circuits (ISIC) December 2009 |
| Q. Chen and G. Csaba and X. Ju and S. B. Natarajan and P. Lugli and M. Stutzmann and U. Schlichtmann and U. Rührmair Analog Circuits for Physical Cryptography International Symposium on Integrated Circuits (ISIC) December 2009 |
| M. Pehl and H. Graeb RaGAzi: A Random and Gradient-Based Approach to Analog Sizing for Mixed Discrete and Continuous Parameters International Symposium on Integrated Circuits (ISIC) December 2009 |
| B. Li and N. Chen and U. Schlichtmann Timing Model Extraction for Sequential Circuits Considering Process Variations IEEE/ACM International Conference on Computer-Aided Design (ICCAD) November 2009 |
| H. Graeb and X. Pan Optimierung integrierter Schaltungen im Hinblick auf Alterungseinfluesse newsletter edacentrum October 2009 |
| M. Eick and M. Strasser and H. Graeb and U. Schlichtmann Automatische Generierung hierarchischer Platzierungsregeln für analoge integrierte Schaltungen GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf September 2009 |
| D. Lorenz and G. Georgakos and U. Schlichtmann Alterungsanalyse digitaler Schaltungen auf Gatterebene GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf September 2009 |
| A. Tchegho and S. Sattler and H. Graeb Walshfunktionen für das Testen von Mixed-Signal Schaltungen GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf September 2009 |
| C. Knoth and V. B. Kleeberger and P. Nordholz and U. Schlichtmann Fast and Waveform Independent Characterization of Current Source Models IEEE/VIUF International Workshop on Behavioral Modeling and Simulation (BMAS) September 2009 |
| E. Avci and M. Strasser and H. Graeb and U. Schlichtmann A Free-Shape Router for Analog and RF Applications European Conference on Circuit Theory and Design (ECCTD) August 2009 |
| D. Mueller-Gritschneder and H. Graeb and U. Schlichtmann A Successive Approach to Compute the Bounded Pareto Front of Practical Multi-objective Optimization Problems SIAM Journal on optimization July 2009 |
| D. Mueller-Gritschneder Deterministic Performance Space Exploration of Analog Integrated Circuits Considering Process Variations and Operating Conditions PhD Thesis June 2009 |
| J. Zou Hierarchical Optimization of Large-Scale Analog/Mixed-Signal Circuits Based-on Pareto-Optimal Fronts PhD Thesis June 2009 |
| A. Tchegho and S. Sattler and H. Graeb Mixed-signal testing using Walsh functions IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW) June 2009 |
| D. Lorenz and G. Georgakos and U. Schlichtmann Aging Analysis of Circuit Timing Considering NBTI and HCI IEEE International On-Line Testing Symposium (IOLTS) June 2009 |
| U. Rührmair and Q. Chen and P. Lugli and U. Schlichtmann and M. Stutzmann and G. Csaba Towards Electrical, Integrated Implementations of SIMPL Systems Cryptology ePrint Archive June 2009 |
| C. Knoth and V. B. Kleeberger and N. Chen and P. Nordholz and U. Schlichtmann Waveform-based Timing Analysis for Digital Circuits using Current Source Models and Model Order Reduction edaWorkshop May 2009 |
| G. Csaba and X. Ju and Q. Chen and W. Porod and J. Schmidhuber and U. Schlichtmann and P. Lugli and U. Rührmair On-Chip Electric Waves: An Analog Circuit Approach to Physical Uncloneable Functions Cryptology ePrint Archive May 2009 |
| B. Li and N. Chen and M. Schmidt and W. Schneider and U. Schlichtmann On Hierarchical Statistical Static Timing Analysis Design, Automation and Test in Europe (DATE) April 2009 |
| M. Strasser and H. Graeb and U. Schlichtmann Plantage - A Deterministic Analog Placement Approach Design, Automation and Test in Europe (DATE) University Booth April 2009 |
| H. Graeb and D. Mueller-Gritschneder and U. Schlichtmann Pareto Optimization of Analog Circuits considering Variability International Journal of Circuit Theory and Applications March 2009 |
| H. Graeb and F. Balasa and R. Castro-Lopez and Y. Chang and F. V. Fernandez and P. Lin and M. Strasser Analog Layout Synthesis - Recent Advances in Topological Approaches Design, Automation and Test in Europe (DATE) 2009 |
| E. Barke and D. Grabowski and H. Graeb and L. Hedrich and S. Heinen and R. Popp and S. Steinhorst and Y. Wang Formal Approaches to Analog Circuit Verification Design, Automation and Test in Europe (DATE) 2009 |
| A. Tchegho and H. Mattes and S. Sattler and H. Graeb Analyse und Untersuchung der Quantisierungseffekte beim Goertzel-Filter Advances in Radio Science - Kleinheubacher Berichte 2009 |
2008
| M. Schmidt Waveform Based Statistical Timing Analysis of Integrated Digital Circuits PhD Thesis December 2008 |
| T. Massier and H. Graeb and U. Schlichtmann The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems December 2008 |
| M. Strasser and M. Eick and H. Graeb and U. Schlichtmann and F. M. Johannes Deterministic Analog Circuit Placement using Hierarchically Bounded Enumeration and Enhanced Shape Functions IEEE/ACM International Conference on Computer-Aided Design (ICCAD) November 2008 |
| M. Pehl and T. Massier and H. Graeb and U. Schlichtmann A Random and Pseudo-Gradient Approach for Analog Circuit Sizing with Non-Uniformly Discretized Parameters IEEE International Conference on Computer Design (ICCD) October 2008 |
| C. Knoth and V. B. Kleeberger and M. Schmidt and B. Li and U. Schlichtmann Transfer System Models of Logic Gates for Waveform-based Timing Analysis International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD) October 2008 |
| B. Li and C. Knoth and M. Schmidt and W. Schneider and U. Schlichtmann Static Timing Model Extraction for Combinational Circuits International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) September 2008 |
| W. Schneider and M. Schmidt and B. Li and U. Schlichtmann A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) September 2008 |
| P. Spindler and U. Schlichtmann and F. M. Johannes Kraftwerk2 -- A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems August 2008 |
| P. Spindler Efficient Quadratic Placement of VLSI Circuits PhD Thesis June 2008 |
| M. Strasser and M. Eick and H. Graeb and F. M. Johannes and U. Schlichtmann Ein hierarchisches Platzierungsverfahren für analoge Schaltungen edaWorkshop May 2008 |
| M. Schmidt and H. Kinzelbach and U. Schlichtmann Genauere Laufzeitanalyse digitaler Schaltungen durch Berücksichtigung statistischer Schwankungen der Signalformen edaWorkshop May 2008 |
| P. Spindler and U. Schlichtmann and F. M. Johannes Abacus: Fast Legalization of Standard Cell Circuits with Minimal Movement ACM/SIGDA International Symposium on Physical Design (ISPD) April 2008 |
| C. Knoth and D. Platte and T. Halfmann and J. Broz and P. Rotter Generierung effizienter Verhaltensmodelle mittels Modellkompilierung und Modellreduktion ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG) April 2008 |
| M. Pehl and T. Massier and H. Graeb and U. Schlichtmann Optimierung analoger Schaltungen mit geordneten diskret veränderlichen Parametern ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG) April 2008 |
| H. Graeb and D. Mueller and U. Schlichtmann Pareto-Optimierung analoger Schaltungen mit Parametertoleranzen ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG) April 2008 |
| T. Massier and H. Graeb and U. Schlichtmann Sizing Rules for Bipolar Analog Circuit Design Design, Automation and Test in Europe (DATE) March 2008 |
| M. Schmidt and H. Kinzelbach and U. Schlichtmann Variational Waveform Propagation for Accurate Statistical Timing Analysis ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems February 2008 |
| V. Esen A New Assertion Language Covering Multiple Levels of Abstraction PhD Thesis 2008 |
| A. Tchegho and H. Mattes and S. Sattler Optimal high-resolution spectral analyzer Design, Automation and Test in Europe (DATE) 2008 |
| T. Massier and H. Graeb Dimensionierungsregeln für analoge Bipolarschaltungen ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG) 2008 |
| A. Tchegho and H. Mattes and S. Sattler Optimaler hochauflösender Spektralanalysator ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG) 2008 |
2007
| G. Stehr and H. Graeb and K. Antreich Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems October 2007 |
| J. Zou and D. Mueller and H. Graeb and U. Schlichtmann Optimization of SC ΣΔ Modulators based on Worst-Case-Aware Pareto-Optimal Fronts IEEE Custom Integrated Circuits Conference (CICC) September 2007 |
| M. Schmidt and B. Li and W. Schneider and H. Kinzelbach and U. Schlichtmann Statistical Timing Analysis using Weibull Waveform Modeling International Symposium on Integrated Circuits (ISIC) September 2007 |
| P. Spindler and F. M. Johannes Kraftwerk --- A Fast and Robust Quadratic Placer Using an Exact Linear Net Model Modern Circuit Placement --- Best Practices and Results September 2007 |
| H. Graeb and D. Mueller and U. Schlichtmann Pareto Optimization of Analog Circuits considering Variability European Conference on Circuit Theory and Design (ECCTD) August 2007 |
| C. Grimm and R. Jahnke and L. Hedrich and S. Huss and H. Graeb Struktursynthese von Analogen und Mixed-Signal Schaltungen: Schwarze Magie? edaWorkshop June 2007 |
| W. Schneider and B. Li and M. Schmidt and U. Schlichtmann A New Bounding Technique for Handling Arbitrary Correlations in Path-Based Statistical STA edaWorkshop June 2007 |
| P. Spindler and F. M. Johannes Fast and Accurate Routing Demand Estimation for Efficient Routability-driven Placement Design, Automation and Test in Europe (DATE) April 2007 |
| D. Mueller and H. Graeb and U. Schlichtmann Trade-Off Design of Analog Circuits using Goal Attainment and Wave Front Sequential Quadratic Programming Design, Automation and Test in Europe (DATE) April 2007 |
| W. Schneider and M. Schmidt and U. Schlichtmann Statistische Laufzeitmodellierung digitaler Gatter mittels analytischem Timing-Modell und Dichte-Transformationssatz GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf March 2007 |
| J. Zou and D. Mueller and H. Graeb and U. Schlichtmann Pareto-Front Computation and Automatic Sizing of CPPLLs IEEE International Symposium on Quality Electronic Design March 2007 |
| H. Graeb and J. Zou and D. Mueller and U. Schlichtmann Hierarchische Optimierung einer Phasenregelschaltung ASIM/GI-Fachgruppentagung Simulation technischer Systeme/Grundlagen und Methoden in Modellbildung und Simulation February 2007 |
| H. Graeb Analog Design Centering and Sizing Springer 2007 |
| U. Schlichtmann and H. Graeb Integrated circuit design: dealing with variations PAMM Proc. Appl. Math. Mech. 2007 |
2006
| D. Mueller and H. Graeb and U. Schlichtmann Optimierung analoger Schaltungsbloecke mittels Pareto-Wellenfront-Optimierung ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG) September 2006 |
| M. Buehler and J. Koehl and J. Bickford and J. Hibbeler and U. Schlichtmann and R. Sommer and M. Pronath and A. Ripp DFM/DFY Design for Manufacturability and Yield - Influence of Process Variations in Digital, Analog and Mixed-Signal Circuit Design Design, Automation and Test in Europe (DATE) May 2006 |
| J. Zou and D. Mueller and H. Graeb and U. Schlichtmann A CPPLL Hierarchical Optimization Methodology Considering Jitter, Power and Locking Time ACM/IEEE Design Automation Conference (DAC) 2006 |
| U. Schlichtmann Statistical Design for Digital Circuits: Statistical Static Timing Analysis (SSTA) Design, Automation and Test in Europe (DATE) 2006 |
| D. Mueller and G. Stehr and H. Graeb and U. Schlichtmann Fast Evaluation of Analog Circuit Structures by Polytopal Approximations IEEE International Symposium on Circuits and Systems (ISCAS) 2006 |
| P. Spindler and F. M. Johannes Fast and Robust Quadratic Placement based on an Accurate Linear Net Model IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2006 |
2005
| D. Mueller and G. Stehr and H. Graeb and U. Schlichtmann Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen Informatik 2005, Beiträge der 35 Jahrestagung der Gesellschaft für Informatik September 2005 |
| J. Zou and D. Mueller and H. Graeb and U. Schlichtmann and E. Hennig and R. Sommer Fast Automatic Sizing of a Charge Pump Phase-Locked Loop based on Behavioral Models Proceeding of IEEE International Behavioral Modeling and Simulation workshop 2005 September 2005 |
| D. Mueller and G. Stehr and H. Graeb and U. Schlichtmann Deterministic Approaches to Analog Performance Space Exploration (PSE) ACM/IEEE Design Automation Conference (DAC) June 2005 |
| B. Obermeier Mehrzieloptimierung beim Plazieren integrierter Schaltungen PhD Thesis March 2005 |
| G. Stehr On the Performance Space Exploration of Analog Integrated Circuits PhD Thesis 2005 |
| M. Pronath Test Design for Analog Integrated Circuits PhD Thesis 2005 |
| U. Seidl Layout-basiertes Retiming für FPGAs PhD Thesis 2005 |
| B. Obermeier and H. Ranke and F. M. Johannes Kraftwerk --- A Versatile Placement Approach ACM/SIGDA International Symposium on Physical Design (ISPD) 2005 |
| A. Frey and M. Schienle and C. Paulus and J. Zou and F. Hofmann and P. Schindler-Bauer and B. Holzapfl and M. Atzesberger and G. Beer and M. Fritz and T. Haneder and H. Hanke and R. Thewes A Digital CMOS DNA Chip IEEE International Symposium on Circuits and Systems (ISCAS) 2005 |
| G. Stehr and H. Graeb and K. Antreich Ein linearer Ansatz zur effizienten Abschätzung der Leistungsfähigkeit analoger Schaltungen ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG) 2005 |
2004
| G. Stehr and H. Graeb and K. Antreich Analog Performance Space Exploration by Fourier-Motzkin Elimination with Application to Hierarchical Sizing IEEE/ACM International Conference on Computer-Aided Design (ICCAD) November 2004 |
| U. Schlichtmann and H. Graeb and R. Sommer and E. Hennig and F. Schenkel and T. Ifström Systematic Analog/Mixed-Signal Design -- Yield Optimization of Analog Circuits with WiCkeD MEDEA Forum November 2004 |
| U. Schlichtmann Design Methodology Innovations Address Manufacturing Technology Challenges: Power and Performance (Invited Paper) EUROMICRO Conference August 2004 |
| B. Obermeier and F. M. Johannes Quadratic Placement Using an Improved Timing Model ACM/IEEE Design Automation Conference (DAC) June 2004 |
| B. Obermeier and F. M. Johannes Temperature-Aware Global Placement Asia and South Pacific Design Automation Conference January 2004 |
| V. Glöckel Entwurfsverfahren zum impliziten funktionalen Test analoger integrierter Schaltungen PhD Thesis 2004 |
| C. Heer and U. Schlichtmann Ultra Low-Power Design: Device and Logic Design Approaches Ultra Low-Power Electronics and Design 2004 |
2003
| T. Massier and G. Stehr and H. Graeb Ein Beitrag zur Automatisierung der Strukturanalyse und der impliziten Spezifikation von analogen integrierten Schaltungen 7. GMM/ITG Diskussionssitzung Entwurf von Analogschaltungen (ANALOG '03) June 2003 |
| A. Kölbl Verifikation digitaler Schaltungen mittels symbolischer Simulation PhD Thesis 2003 |
| F. Schenkel Tolerance Analysis and Design Centering of Analog Circuits with Consideration of Mismatch PhD Thesis 2003 |
| K. Eckl Technologienahe Retimingverfahren zur Optimierung synchroner digitaler Schaltungen PhD Thesis 2003 |
| G. Stehr and H. Graeb and K. Antreich Performance Trade-off Analysis of Analog Circuits By Normal-Boundary Intersection ACM/IEEE Design Automation Conference (DAC) 2003 |
| U. Seidl and K. Eckl and F. Johannes Performance-directed Retiming for FPGAs using Post-placement Delay Information Design, Automation and Test in Europe (DATE) 2003 |
| U. Seidl and K. Eckl and F. Johannes Layout-basiertes Retiming für FPGAs Entwurf Integrierter Schaltungen (E.I.S.-Workshop) 2003 |
| G. Stehr and M. Pronath and F. Schenkel and H. Graeb and K. Antreich Initial Sizing of Analog Integrated Circuits by Centering within Topology-Given Implicit Specifications IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2003 |
| G. Stehr and H. Graeb and K. Antreich Untersuchung der Leistungsfähigkeit analoger Schaltungen mit Hilfe von Dimensionierungsregeln und nichtlinearer Mehrziel-Optimierung ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG) 2003 |
| G. Stehr and H. Graeb and K. Antreich Hierarchische Simulation von Mixed-Signal-Schaltungen Informationstagung Mikroelektronik 2003 (ME '03) 2003 |
| M. Pronath and H. Graeb and K. Antreich On Parametric Test Design for Analog Integrated Circuits considering Error in Measurement and Stimulus Modeling, Simulation and Optimization of Integrated Circuits 2003 |
| K. J. Antreich and H. Graeb Circuit Optimization driven by Worst-Case Distances The Best of ICCAD - 20 Years of Excellence in Computer-Aided Design 2003 |
| G. Stehr and H. Graeb and K. Antreich Feasibility Regions and their Significance to the Hierarchical Optimization of Analog and Mixed-Signal Systems International Series of Numerical Mathematics 2003 |
2002
| M. Senn and U. Seidl and F. Johannes High Quality Deterministic Timing Driven FPGA Placement ACM/SIGDA International Symposium on Field-Programmable Gate Arrays February 2002 |
| M. A. Senn Plazierverfahren für anwenderprogrammierbare Logikbausteine (FPGAs) PhD Thesis 2002 |
| N. Fröhlich Verfahren zum Schaltungspartitionieren für die parallele Simulation auf Transistorebene PhD Thesis 2002 |
| R. Schwencker Zur Dimensionierung analoger integrierter Schaltungen unter Berücksichtigung struktureller Nebenbedingungen PhD Thesis 2002 |
| A. Kölbl and J. Kukula and K. Antreich and R. Damiano Handling Special Constructs in Symbolic Simulation ACM/IEEE Design Automation Conference (DAC) 2002 |
| F. Schenkel and M. Pronath and H. Graeb WiCkeD 3: Design Centering and Mismatch Analysis for Analog Integrated Circuits Design, Automation and Test in Europe (DATE 02) Designers' Forum 2002 |
| R. Schwencker and F. Schenkel and M. Pronath and H. Graeb Analog Circuit Sizing using Adaptive Worst-Case Parameter Sets Design, Automation and Test in Europe (DATE) 2002 |
| M. Pronath and H. Graeb and K. Antreich A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits Design, Automation and Test in Europe (DATE) 2002 |
| U. Schlichtmann Systems are made from Transistors: UDSM Technology Creates New Challenges for Library and IC Developement Digital System Design Symposium 2002 |
| H. Graeb and S. Zizala and J. Eckmüller and K. Antreich Eine Systematik von Dimensionierungsregeln für den Entwurf analoger integrierter Schaltungen GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden 2002 |
| R. Schwencker and F. Schenkel and M. Pronath and H. Graeb Dimensionierung analoger integrierter Schaltungen mittels adaptiver Worst-Case-Parametersätze GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden 2002 |
| M. Pronath and H. Graeb and K. Antreich Simulation und Testentwurf für ,,Floating-Gate`` Defekte (FGD) in analogen integrierten Schaltungen GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden 2002 |
| M. Pronath and H. Graeb and K. Antreich Design of Optimal Inplicit Tests for Parametric Faults considering Errors of Test Stimuli and of Measurements IEEE European Test Workshop (ETW) 2002 |
| M. Pronath and H. Graeb and K. Antreich Der Einfluss von Ungenauigkeiten im Teststimulus auf den Test analoger Schaltungen ITG/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen 2002 |
| G. Stehr and H. Graeb and K. Antreich Dimensionierungsnebenbedingungen bei der hierarchischen Optimierung von Mixed-Signal-Systemen ITG/GMM-Fachtagung Entwurf von analogen Schaltungen mit CAE-Methoden (ANALOG) 2002 |
2001
| G. Stehr and H. Graeb and K. Antreich A Hierarchical Optimization Approach for Analog and Mixed-Signal Systems Forum on Design Languages (FDL) September 2001 |
| M. Senn and B. Obermeier and F. M. Johannes Ein Ein-Schritt-Plazierverfahren für FPGAs Entwurf Integrierter Schaltungen (E.I.S.-Workshop) April 2001 |
| B. Obermeier and F. M. Johannes and V. M. z. Bexten Floorplanning/Plazieren für mixed-signal SoCs Entwurf Integrierter Schaltungen (E.I.S.-Workshop) April 2001 |
| V. Glöckel and M. Pronath and H. Graeb Deterministischer parametrischer Testentwurf für analoge integrierte Schaltungen mit Testbeobachtungen unter Anwendung von Ergebnissen aus dem Toleranzentwurf ITG/GMM/GI Testmethoden und Zuverlässigkeit von Schaltungen und Systemen February 2001 |
| P. Tafertshofer Test Pattern Generation and Verification for Logic Circuits PhD Thesis 2001 |
| S. Zizala Numerische Verhaltensmodellierung analoger CMOS-Schaltungen unter Berücksichtigung von Dimensionierungsregeln PhD Thesis 2001 |
| P. Tafertshofer Test Pattern Generation and Verification for Logic Circuits PhD Thesis 2001 |
| F. Schenkel and M. Pronath and S. Zizala and R. Schwencker and H. Graeb and K. Antreich Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search ACM/IEEE Design Automation Conference (DAC) 2001 |
| A. Kölbl and J. Kukula and R. Damiano Symbolic RTL Simulation ACM/IEEE Design Automation Conference (DAC) 2001 |
| F. Schenkel and M. Pronath and H. Graeb and K. Antreich A Fast Method for Identifying Matching-Relevant Transistor Pairs IEEE Custom Integrated Circuits Conference (CICC) 2001 |
| M. Senn and U. Seidl and F. Johannes A Two Phase Approach to Timing Driven FPGA Placement IEEE International Conference on Computer Design (ICCD) 2001 |
| M. Pronath and H. Graeb and K. Antreich Estimation of the Influence of Test Stimulus Precision on Test Quality for Parametric Faults in Analog Integrated Circuits IEEE International Workshop on Mixed Signal Testing 2001 |
| H. Graeb and S. Zizala and J. Eckmueller and K. Antreich The Sizing Rules Method for Analog Integrated Circuit Design IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2001 |
2000
| K. Antreich and J. Eckmüller and H. Graeb and M. Pronath and F. Schenkel and R. Schwencker and S. Zizala WiCkeD: Analyse und Dimensionierung analoger Schaltungen unter Berücksichtigung von Mismatch ITG Workshop Mikroelektronik für die Informationstechnik November 2000 |
| J. Eckmüller and R. Jancke and S. Zizala and P. Trappe and P. Schwarz Eine Methodik zur Modellierung komplexer Mixed-Signal Baugruppen Abschluss-Workshop des Smart-Systems-Engineering(SSE)-Projekts Verhaltensmodellierung, Mixed-Signal-Modellierung und Simulation (HDL) October 2000 |
| R. Schwencker and C. Sporrer and H. Graeb A Method for the Generation of Declarative Models for Interface Circuits Symbolic Methods and Applications in Circuit Design (SMACD) October 2000 |
| A. Ganz and P. Tafertshofer Parallel Path Classification for Path Delay Fault Testing and Timing Analysis European Conference on Parallel Computing (Euro-Par) August 2000 |
| P. Tafertshofer and A. Ganz and K. Antreich IGRAINE - an Implication GRaph bAsed engINE for fast implication, justification, and propagation IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems August 2000 |
| J. Fleischmann Codesign of Hardware/Software Systems Based on Java PhD Thesis July 2000 |
| K. Antreich and J. Eckmueller and H. Graeb and M. Pronath and F. Schenkel and R. Schwencker and S. Zizala WiCkeD: Analog Circuit Synthesis Incorporating Mismatch IEEE Custom Integrated Circuits Conference (CICC) May 2000 |
| N. Fröhlich and V. Glöckel and J. Fleischmann A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level Design, Automation and Test in Europe (DATE) March 2000 |
| R. Schwencker and F. Schenkel and H. Graeb and K. Antreich The Generalized Boundary Curve -- A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits Design, Automation and Test in Europe (DATE) March 2000 |
| G. Stenz and B. M. Riess and B. Rohfleisch and F. M. Johannes Performance Optimization by Interacting Netlist Transformations and Placement IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems March 2000 |
| R. Kress and K. Buchenrieder and J. Fleischmann Codesign of Networked Embedded Systems Embedded Intelligence Conference February 2000 |
| R. Kress and K. Buchenrieder and J. Fleischmann Java-basiertes Codesign Elektronik Praxis February 2000 |
| K. Antreich Ein Puzzle aus 10 Million Teilen forschung - Das Magazin der Deutschen Forschungsgemeinschft (DFG) February 2000 |
| M. Pronath and V. Glöckel and H. Graeb and K. Antreich Testentwurf für analoge Komponenten gemischt analog-digitaler Schaltungen basierend auf dem Übertragungsverhalten Architekturentwurf für eingebettete Systeme (AES) January 2000 |
| A. Ganz Effiziente Verfahren zu Analyse und Test von Laufzeiteigenschaften integrierter Schaltungen PhD Thesis 2000 |
| G. Stenz Verfahren zur Optimierung von Signallaufzeiten bei der Layoutsynthese integrierter Schaltungen PhD Thesis 2000 |
| M. Pronath and V. Gloeckel and H. Graeb A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2000 |
| N. Fröhlich and V. Glöckel and G. Denk A New Multi-Way partitioning Method for Parallel Circuit Simulation SFB 342 Methods and Tools for the Efficient Use of Parallel Systems 2000 |
| A. Ganz and P. Tafertshofer Parallel Path Classification for Path Delay Fault Testing and Timing Analysis SFB 342 Methods and Tools for the Efficient Use of Parallel Systems 2000 |
1999
| R. Schlagenhaft Dynamischer Lastausgleich verteilter diskreter Simulation PhD Thesis December 1999 |
| P. Tafertshofer and A. Ganz SAT Based ATPG Using Fast Justification and Propagation in the Implication Graph IEEE/ACM International Conference on Computer-Aided Design (ICCAD) November 1999 |
| R. Jancke and S. Zizala and J. Eckmüller and P. Trappe Modellierung komplexer Baugruppen Smart System Engineering -- HDL-VMS-Statusseminar November 1999 |
| W. M. Lindermeir and H. Graeb and K. J. Antreich Analog Testing by Characteristic Observation Inference IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems September 1999 |
| B. Wurth and U. Schlichtmann and K. Eckl and K. J. Antreich Functional Multiple-Output Decomposition with Application to Technology Mapping for Lookup Table-Based FPGAs ACM Transactions on Design Automation of Electronic Systems July 1999 |
| H. Eisenmann Ein universelles Plazierverfahren für integrierte Schaltungen PhD Thesis June 1999 |
| J. Fleischmann and K. Buchenrieder and R. Kress Java Driven Codesign and Prototyping of Networked Embedded Systems ACM/IEEE Design Automation Conference (DAC) June 1999 |
| K. Eckl and J. C. Madre and P. Zepter and C. Legl A Practical Approach to Multiple-Class Retiming ACM/IEEE Design Automation Conference (DAC) June 1999 |
| P. Tafertshofer and A. Ganz ATPG Using Fast Justification and Propagation on the Implication Graph IEEE European Test Workshop (ETW) May 1999 |
| J. Eckmüller and S. Zizala and A. Schwaferts Modellierung analoger Schaltungsblöcke Workshop zum Förderschwerpunkt Smart System Engineering April 1999 |
| A. Ganz and P. Tafertshofer An Efficient Framework for Functional Path Analysis ACM/IEEE Int. Workshop on Timing Issues in the Spec. and Syn. of Dig. Systems March 1999 |
| R. Schwencker and J. Eckmüller and H. Graeb and K. Antreich Automating the Sizing of Analog CMOS-Circuits by Consideration of Structural Constraints Design, Automation and Test in Europe (DATE) March 1999 |
| J. Fleischmann and K. Buchenrieder and R. Kress Codesign of Embedded Systems based on Java and Reconfigurable Hardware Components Design, Automation and Test in Europe (DATE) March 1999 |
| K. Eckl and C. Legl Retiming Sequential Circuits with Multiple Register Classes Design, Automation and Test in Europe (DATE) March 1999 |
| M. Pronath and V. Glöckel and H. Graeb and K. Antreich Simulationsbasierter Testentwurf für gemischt analog-digitale Systeme it+ti, Informationstechnik und Technische Informatik March 1999 |
| C. Legl Logiksynthese für wertetabellenbasierte anwenderprogrammierbare Bausteine PhD Thesis February 1999 |
| R. Schwencker and J. Eckmüller and H. Graeb and K. Antreich Automatische Nominalpunktdimensionierung analoger CMOS-Schaltungen mit Parameterabständen als Zielgrößen GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden February 1999 |
| A. Ganz and P. Tafertshofer Effiziente Verfahren zur funktionalen Pfadanalyse ITG/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen February 1999 |
| J. Fleischmann and K. Buchenrieder Prototyping Networked Embedded Systems IEEE Computer February 1999 |
| A. Lu and G. Stenz and H. Eisenmann and F. M. Johannes Technology Mapping for Simultaneous Gate and Interconnect Optimisation IEE Proceedings -- Computers and Digital Techniques January 1999 |
| R. Schwencker and F. Schenkel and H. Graeb and K. Antreich Automatische Entwurfszentrierung analoger integrierter Komponenten basierend auf der Verallgemeinerten Grenzkurve von Mehrfach-Robustheits-Maßen Entwurf Integrierter Schaltungen (E.I.S.-Workshop) 1999 |
| R. Schlagenhaft Dynamischer Lastausgleich optimistisch synchronisierter, verteilter Simulation GI-Workshop Verteilte Simulation und parallele Prozesse 1999 |
| C. Sporrer and R. Schwencker and T. Latzel and H. Graeb Generierung und Anwendungen von deklarativen Modellen für Treiberschaltungen GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden 1999 |
| S. Zizala and J. Eckmüller and H. Graeb Effiziente Modellierung integrierter analoger CMOS-Schaltungen durch Berücksichtigung von Struktureigenschaften GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden 1999 |
| F. Schenkel and H. Graeb and K. Antreich Ausbeuteanalyse unter Berücksichtigung lokaler und globaler Parameterschwankungen GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden 1999 |
1998
| M. K. Ruhwandl Simulation von Verbindungsleitungsnetzen in integrierten Schaltungen mit Berücksichtigung der nichtlinearen Eigenschaften des Treibers PhD Thesis October 1998 |
| A. Lu and H. Eisenmann and G. Stenz and F. M. Johannes Combining Technology Mapping with Post-Placement Resynthesis for Performance Optimization IEEE International Conference on Computer Design (ICCD) October 1998 |
| R. Schwencker and H. Graeb and T. Latzel and C. Sporrer Interface Circuits and Symbolic Analysis Symbolic Methods and Applications in Circuit Design (SMACD) October 1998 |
| J. Fleischmann and K. Buchenrieder and R. Kress Co-Design of Reconfigurable Embedded Systems based on JAVA Specification GI/ITG Workshop Java und eingebettete Systeme September 1998 |
| S. Zizala and J. Eckmueller and H. Graeb Fast Calculation of Analog Circuits' Feasibility Regions by Low Level Functional Measures IEEE Int. Conf. on Electronics, Circuits and Systems September 1998 |
| C. Legl and B. Wurth and K. Eckl Computing Support-Minimal Subfunctions During Functional Decomposition IEEE Transactions on VLSI Systems September 1998 |
| H. Eisenmann and F. M. Johannes Generic Global Placement and Floorplanning ACM/IEEE Design Automation Conference (DAC) June 1998 |
| N. Fröhlich and B. M. Riess and U. A. Wever and Q. Zheng A New Approach for Parallel Simulation of VLSI Circuits on a Transistor Level IEEE Transactions on Circuits and Systems CAS June 1998 |
| G. Strube Robuste Verfahren zur Worst-Case- und Ausbeute-Analyse analoger integrierter Schaltungen PhD Thesis April 1998 |
| J. Fleischmann and K. Buchenrieder and R. Kress A Hardware/Software Prototyping Environment for Dynamically Reconfigurable Embedded Systems IEEE Int. Workshop on Hardware/Software Codesign March 1998 |
| W. M. Lindermeir and T. J. Vogels and H. Graeb Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults Design, Automation and Test in Europe (DATE) February 1998 |
| A. Lu and G. Stenz and F. M. Johannes Technology Mapping for Minimizing Gate and Routing Area Design, Automation and Test in Europe (DATE) February 1998 |
| J. Eckmueller and M. Groepl and H. Graeb Hierarchical Characterization of Analog Integrated CMOS Circuits Design, Automation and Test in Europe (DATE) February 1998 |
| J. Eckmüller Zur rechnergestützten Dimensionierung analoger integrierter Schaltungen unter besonderer Berücksichtigung von Struktureigenschaften PhD Thesis January 1998 |
| M. Eisele Einfluß von Parameterschwankungen auf die Ausbeute digitaler Niedervoltschaltungen PhD Thesis 1998 |
1997
| P. Tafertshofer and A. Ganz and M. Henftling A SAT-Based Implication Engine for Efficient ATPG, Equivalence Checking, and Optimization of Netlists IEEE/ACM International Conference on Computer-Aided Design (ICCAD) November 1997 |
| A. Ganz Automatic Test Pattern Generation Dynamic Load Distribution for Parallel Applications September 1997 |
| R. Schlagenhaft MPSIM - Parallel Event Driven Simulation of Logic Circuits by Time Warp Dynamic Load Distribution for Parallel Applications September 1997 |
| X. Lin and E. Dagless and A. Lu Technology Mapping of LUT based FPGAs for Delay Optimisation International Workshop on Field-Programmable Logic and Applications (FPL) September 1997 |
| N. Fröhlich and R. Schlagenhaft and J. Fleischmann A New Approach for Partitioning VLSI Circuits on Transistor Level ACM/SCS/IEEE Workshop on Parallel and Distributed Simulation (PADS) June 1997 |
| T. Schnekenburger and G. Stenz and H. Spruth Problem-Oriented Parallelization of an Iterative Placement Algorithm International Conference on Parallel and Distributed Processing Techniques and Applications June 1997 |
| A. Ganz and P. Tafertshofer and H. Wittmann Statistical Analysis of Delay Faults IEEE European Test Workshop (ETW) May 1997 |
| C. Legl and P. Vanbekbergen and A. Wang Retiming of Edge-Triggered Circuits with Multiple Clocks and Load Enables International Workshop on Logic Synthesis (IWLS) May 1997 |
| A. Kölbl and B. Wurth A New Method for the Approximate Computation of Observability Relations International Workshop on Logic Synthesis (IWLS) May 1997 |
| P. Tafertshofer and C. Ebner and A. Ganz and M. Henftling A SAT-Based Implication Engine for Efficient Derivation of Indirect Implications International Workshop on Logic Synthesis (IWLS) May 1997 |
| K. Eckl and C. Legl and B. Wurth An Implicit Approach to Functional Decomposition of Incompletely Specified Boolean Functions International Workshop on Logic Synthesis (IWLS) May 1997 |
| K. Antreich and A. Ganz and P. Tafertshofer Statistical Analysis of Delay Faults - Theory and Efficient Computation Archiv für Elektronik und Übertragungstechnik (AEÜ) May 1997 |
| G. Stenz and B. M. Riess and B. Rohfleisch and F. M. Johannes Timing Driven Placement in Interaction with Netlist Transformations ACM/SIGDA International Symposium on Physical Design (ISPD) April 1997 |
| P. Tafertshofer and M. Pedram Factored Edge-Valued Binary Decision Diagrams Formal Methods in System Design April 1997 |
| J. Fleischmann and R. Schlagenhaft and M. Peller and N. Fröhlich OLIVIA: Objectoriented Logicsimulation Implementing the VITAL Standard Great Lakes Symposium on VLSI (GLS-VLSI) March 1997 |
| W. M. Lindermeir and T. Vogels and H. Graeb Erkennung parametrischer Fehler mittels IDD-Messungen in analogen integrierten Schaltungen ITG/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen March 1997 |
| J. Fleischmann and R. Schlagenhaft and M. Peller Objektorientierte Logiksimulation nach dem VITAL Standard ITG/GI/GMM-Workshop Hardwarebeschreibungssprachen und Modellierungsparadigmen February 1997 |
| P. Tafertshofer and A. Ganz and M. Henftling Reducing the Complexity of Path Classification by Reconvergence Analysis Asia and South Pacific Design Automation Conference January 1997 |
| W. M. Lindermeir Testentwurf für analoge integrierte Schaltungen mit charakteristischen Beobachtungen PhD Thesis 1997 |
| B. Rohfleisch Optimierung von Netzlisten kombinatorischer Schaltungen PhD Thesis 1997 |
| M. Hermann Technologieabbildung und Testvorbereitung für programmierbare Logikbausteine mit komplexen Grundzellen PhD Thesis 1997 |
| N. Fröhlich and R. Schlagenhaft and A. Ganz and J. Fleischmann Object Orientation in Time Warp Simulation International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA) 1997 |
1996
| W. M. Lindermeir Design of Robust Test Criteria in Analog Testing IEEE/ACM International Conference on Computer-Aided Design (ICCAD) November 1996 |
| J. Eckmüller and G. Strube and H. Graeb Diagnose für integrierte Analogschaltungen GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden October 1996 |
| H. Graeb and G. Müller-Liebler and G. Strube WiCkeD: Worst-Case- und Ausbeute-Analyse GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden October 1996 |
| W. M. Lindermeir and H. Graeb Entwurf robuster Testkriterien für das Prüfen analoger integrierter Schaltungen GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden October 1996 |
| M. K. Ruhwandl and H. Graeb Schnelle Interconnectsimulation von RLC-Leitungen mit Berücksichtigung von Treibernichtlinearitäten GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden October 1996 |
| G. Strube and J. Eckmüller and H. Graeb Zuverlässige Empfindlichkeitsberechnung für die Analogoptimierung GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden October 1996 |
| W. Eisenmann and H. Graeb Modellierung der Verlustleistung, der Zuverlässigkeit und der elektromagnetischen Verträglicheit für die Logiksimulation GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden October 1996 |
| T. H. Abthoff and F. M. Johannes TINA: Analog Placement using Enumerative Techniques Capable of Optimizing both Area and Net Length European Design Automation Conference with EURO-VHDL (EURO-DAC) September 1996 |
| P. H. Schneider and M. A. Senn and B. Wurth Power Analysis for Sequential Circuits at Logic Level European Design Automation Conference with EURO-VHDL (EURO-DAC) September 1996 |
| C. Legl and K. Eckl and B. Wurth Performance-Directed Technology Mapping for LUT-based FPGAs -- What Role Do Decomposition and Covering Play? International Workshop on Field-Programmable Logic and Applications (FPL) September 1996 |
| P. H. Schneider and S. Krishnamoorthy Effect of Correlations on Accuracy of Power Analysis - An Experimental Study IEEE/ACM/SIGDA International Symposium on Low Power Electronics and Design August 1996 |
| M. Eisele and J. Berthold and D. Schmitt-Landsiedel and R. Mahnkopf The Impact of Intra-Die Device Parameter Variations on Path Delays and on the Design for Yield of Low Voltage Digital Circuits IEEE/ACM/SIGDA International Symposium on Low Power Electronics and Design August 1996 |
| B. Rohfleisch and A. Kölbl and B. Wurth Reducing Power Dissipation after Technology Mapping by Structural Transformations ACM/IEEE Design Automation Conference (DAC) June 1996 |
| C. Legl and B. Wurth and K. Eckl A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs ACM/IEEE Design Automation Conference (DAC) June 1996 |
| F. M. Johannes Partitioning of VLSI Circuits and Systems ACM/IEEE Design Automation Conference (DAC) June 1996 |
| W. M. Lindermeir Auswahl signifikanter Meßgrößen für das Testen analoger Schaltungen GI/GMM/ITG Workshop Methoden und Werkzeuge zum Entwurf von Mikrosystemen June 1996 |
| W. M. Lindermeir Feature Extraction for Measurement Selection in Analog Testing IEEE International Workshop on Mixed Signal Testing May 1996 |
| C. Legl and B. Wurth and K. Eckl An Implicit Algorithm For Support Minimization During Functional Decomposition European Design and Test Conference (EDTC) March 1996 |
| M. Eisele and J. Berthold and D. Schmitt-Landsiedel Laufzeitschwankungen von digitalen Schaltungen bei niedrigsten Versorgungsspannungen und minimalen Transistordimensionen ITG-Fachtagung Mikroelektronik für die Informationstechnik March 1996 |
| P. Tafertshofer and M. Henftling and H. Wittmann Ein schnelles Verfahren zur Ermittlung nichtrelevanter Pfade mit Hilfe der Rekonvergenzanalyse ITG/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen March 1996 |
| A. Ganz and M. Henftling and H. Wittmann Zur Berechnung von Verzögerungsdefekt-Wahrscheinlichkeiten ITG/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen March 1996 |
| B. Wurth Logic Synthesis with the Boolean Model PhD Thesis 1996 |
| H. Wittmann Testentwurf zur Erkennung von Verzögerungsfehlern in hochintegrierten Schaltungen PhD Thesis 1996 |
| M. Henftling Berechnung von Testvektoren in digitalen Schaltungen auf der Basis von Klauselsystemen PhD Thesis 1996 |
| T. Abthoff Plazieren der Komponenten integrierter Analogschaltungen 1996 |
| W. Eisenmann Schnelle Simulation der Verlustleistung und der Zuverlässigkeit von hochintegrierten CMOS-Schaltkreisen auf Gatterebene PhD Thesis 1996 |
| P. Schneider Analyse des Leistungsverbrauchs integrierter Schaltungen auf Logikebene PhD Thesis 1996 |
| B. Riess Physical Design for Multichip Modules PhD Thesis 1996 |
| B. M. Riess and A. A. Schoene A New Layout Design System for Multichip Modules High Performance Design Automation for Multi-Chip Modules and Packages 1996 |
| P. H. Schneider and U. Schlichtmann and B. Wurth Fast Power Estimation of Large Circuits IEEE Design and Test 1996 |
1995
| M. Eisele and J. Berthold and R. Thewes and E. Wohlrab and D. Schmitt-Landsiedel and W. Weber Intra-Die Device Parameter Variations and their Impact on Digital CMOS Gates at Low Supply Voltages Int. Electron Devices Meeting December 1995 |
| B. M. Riess and H. Eisenmann Ein Bewertungsverfahren für Plazieralgorithmen Entwurf Integrierter Schaltungen (E.I.S.-Workshop) November 1995 |
| M. Henftling and H. C. Wittmann and K. J. Antreich A Single-Path-Oriented Fault-Effect Propagation in Digital Circuits Considering Multiple-Path Sensitization IEEE/ACM International Conference on Computer-Aided Design (ICCAD) November 1995 |
| W. M. Lindermeir and H. Graeb and K. J. Antreich Design Based Analog Testing by Characteristic Observation Inference IEEE/ACM International Conference on Computer-Aided Design (ICCAD) November 1995 |
| M. Eisele and J. Berthold Dynamic Gate Delay Modeling for Accurate Estimation of Glitch Power at Logic Level International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) October 1995 |
| P. H. Schneider PAPSAS: A Fast Switching Activity Simulator International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) October 1995 |
| M. Henftling and H. Wittmann and K. J. Antreich A Formal Non-Heuristic ATPG Approach European Design Automation Conference with EURO-VHDL (EURO-DAC) September 1995 |
| H. Wittmann and M. Henftling Path Delay ATPG for Standard Scan Designs European Design Automation Conference with EURO-VHDL (EURO-DAC) September 1995 |
| B. M. Riess and H. A. Giselbrecht and B. Wurth A New K-Way Partitioning Approach for Multiple Types of FPGAs Asia and South Pacific Design Automation Conference August 1995 |
| M. Waidelich and R. Lederle A Development System for Fuzzy Hardware European Congress on Intelligent Techniques and Soft Computing (EUFIT) August 1995 |
| R. Lederle and P. Eubert and H. Eichfeld Hardware Architecture for Fuzzy Control of Electric Feed Drive using a Fuzzy Coprocessor and a Transputernetwork European Congress on Intelligent Techniques and Soft Computing (EUFIT) August 1995 |
| T. Abthoff and F. M. Johannes Analogue Placement using Guided Enumeration International Journal of Circuit Theory and Applications July 1995 |
| B. Rohfleisch and B. Wurth and K. Antreich Logic Clause Analysis for Delay Optimization ACM/IEEE Design Automation Conference (DAC) June 1995 |
| B. Wurth and K. Eckl and K. Antreich Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm ACM/IEEE Design Automation Conference (DAC) June 1995 |
| J. Fleischmann and P. A. Wilsey Comparative Analysis of Periodic State Saving Techniques in Time Warp Simulators ACM/SCS/IEEE Workshop on Parallel and Distributed Simulation (PADS) June 1995 |
| R. Schlagenhaft and M. K. Ruhwandl and C. Sporrer and H. Bauer Dynamic Load Balancing of a Multi-Cluster Simulator on a Network of Workstations ACM/SCS/IEEE Workshop on Parallel and Distributed Simulation (PADS) June 1995 |
| B. M. Riess and H. A. Giselbrecht and B. Wurth K-Way Partitioning for Multiple Type FPGAs GI/ITG Workshop Anwenderprogrammierbare Schaltungen June 1995 |
| W. M. Lindermeir and H. Graeb and K. J. Antreich Analog Testing by Equivalent-Performance Matching IEEE International Workshop on Mixed Signal Testing June 1995 |
| R. Lederle and M. Waidelich Fuzzy Logic Entwicklungssystem für den Fuzzy Logic Coprozessor SAE 81C99 VDE/ITG Diskussionssitzung NULLMikroelektronik der Fuzzy-SystemeNULL June 1995 |
| B. Rohfleisch and B. Wurth and K. J. Antreich Delay Optimization of Combinational Circuits by Logic Clause Analysis International Workshop on Logic Synthesis (IWLS) May 1995 |
| P. H. Schneider and B. Wurth Transition Probability Estimation for Combinational and Sequential Circuits International Workshop on Logic Synthesis (IWLS) May 1995 |
| B. Wurth and K. Eckl and K. Antreich Functional Multiple-Output Decomposition for Lookup-Table Based FPGAs International Workshop on Logic Synthesis (IWLS) May 1995 |
| B. M. Riess and G. Ettelt SPEED: Fast and Efficient Timing Driven Placement IEEE International Symposium on Circuits and Systems (ISCAS) April 1995 |
| M. Henftling and H. Wittmann Bit Parallel Test Pattern Generation for Path Delay Faults European Design and Test Conference (EDTC) March 1995 |
| B. Wurth and K. Fuchs A BIST Approach to Delay Fault Testing with Reduced Test Length European Design and Test Conference (EDTC) March 1995 |
| B. M. Riess and A. A. Schoene Architecture Driven K-Way Partitioning for Multichip Modules European Design and Test Conference (EDTC) March 1995 |
| T. Abthoff and F. M. Johannes PLACEBO: Analog Placement with efficient Symmetry Support Archiv für Elektronik und Übertragungstechnik (AEÜ) March 1995 |
| W. W. Lindermeir and H. Graeb On the Production Test of Analog Circuits by Statistical Fault Modeling Archiv für Elektronik und Übertragungstechnik (AEÜ) March 1995 |
| M. Henftling Petri-Netze zur Testmustergenerierung für verschiedene Fehlermodelle ITG/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen February 1995 |
| H. Wittmann Fehlersimulation für Pfadverzögerungsfehler in digitalen Schaltungen mit Standard--Prüfpfad ITG/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen February 1995 |
| P. A. Krauss Parallelisierung der automatischen Testmustergenerierung in sequentiellen Schaltungen PhD Thesis January 1995 |
| M. Hermann and B. Rohfleisch and U. Schlichtmann and B. Wurth Logic Synthesis for Library-Based Field Programmable Gate Arrays Archiv für Elektronik und Übertragungstechnik (AEÜ) January 1995 |
| M. Henftling and H. Wittmann A New Data Structure to Solve the Satisfiability Problem in Digital Circuits Archiv für Elektronik und Übertragungstechnik (AEÜ) January 1995 |
| H. Spruth Parallele Verfahren zur automatischen Layoutsynthese integrierter Schaltungen PhD Thesis 1995 |
| B. Wurth and N. Wehn Multiple-level logic optimization with Boolean relations Novel Approaches in Logic and Architecture Synthesis 1995 |
| B. M. Riess and A. A. Schoene A New Layout Design System for Multichip Modules International Journal of High Speed Electronics and Systems 1995 |
1994
| P. A. Krauss and M. Henftling Efficient Fault Ordering for Automatic Test Pattern Generation for Sequential Circuits IEEE Asian Test Symposium (ATS) November 1994 |
| M. Miura-Mattausch and U. Feldmann and A. Rahm and M. Bollu and D. Savignac Unified Complete MOSFET Model for Analysis of Digital and Analog Circuits IEEE/ACM International Conference on Computer-Aided Design (ICCAD) November 1994 |
| W. T. Eisenmann and H. Graeb Fast Transient Power and Noise Estimation for VLSI Circuits IEEE/ACM International Conference on Computer-Aided Design (ICCAD) November 1994 |
| K. Doll and F. M. Johannes and K. J. Antreich Iterative Placement Improvement by Network Flow Methods IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems October 1994 |
| W. M. Lindermeir and M. K. Ruhwandl and F. Lenke Dimensionierung von balancierten Taktbäumen/Teil 1 designelektronik October 1994 |
| W. M. Lindermeir and M. K. Ruhwandl and F. Lenke Dimensionierung von balancierten Taktbäumen/Teil 2 designelektronik October 1994 |
| R. E. Lederle and P. Eubert and H. Eichfeld Fuzzy Logic Control of Electric Feed Drive of CNC Machine Tools European Congress on Intelligent Techniques and Soft Computing (EUFIT) September 1994 |
| P. H. Schneider and U. Schlichtmann and K. J. Antreich A New Power Estimation Technique with Application to Decomposition of Boolean Functions for Low Power European Design Automation Conference with EURO-VHDL (EURO-DAC) September 1994 |
| G. Strube and H. Graeb ASIS: Automatische Simulator-Steuerung GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden September 1994 |
| M. Eisele and K. Hentschel and T. Künemund Hardware Realization of Fast Defuzzification by Adaptive Integration IEEE International Conference on Microelectronics for Neural Networks and Fuzzy Systems September 1994 |
| M. Hermann and W. Hoffmann Fault Modeling and Test Generation for FPGAs International Workshop on Field-Programmable Logic and Applications (FPL) September 1994 |
| M. Henftling and H. C. Wittmann and K. J. Antreich Path Hashing to Accelerate Delay Fault Simulation ACM/IEEE Design Automation Conference (DAC) June 1994 |
| B. M. Riess and K. Doll and F. M. Johannes Partitioning Very Large Circuits Using Analytical Placement Techniques ACM/IEEE Design Automation Conference (DAC) June 1994 |
| H. Spruth and F. M. Johannes and K. J. Antreich PHIroute: A Parallel Hierarchical Sea-of-Gates Router IEEE International Symposium on Circuits and Systems (ISCAS) May 1994 |
| M. Miura-Mattausch and A. Rahm and M. Bollu and U. Feldmann and D. Savignac A Novel Consistent MOSFET Model for CAD Application with Reduced Calculation Time IEEE International Symposium on Circuits and Systems (ISCAS) May 1994 |
| P. H. Schneider and U. Schlichtmann Synthese zur Minimierung des Leistungsverbrauchs von FPGAs ITG/GME/GI-Fachtagung Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme May 1994 |
| P. H. Schneider and U. Schlichtmann Decomposition of Boolean Function for Low Power Based on a New Power Estimation Technique ACM/IEEE International Workshop on Low Power Design April 1994 |
| H. Spruth and F. M. Johannes Parallel Routing of VLSI Circuits Based on Net Independency IEEE International Parallel Processing Symposium (IPPS) April 1994 |
| P. A. Krauss A Distributed Automatic Test Pattern Generation System Lecture Notes in Computer Science No.~796: High--Performance Computing and Networking April 1994 |
| B. Rohfleisch and F. Brglez Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping European Design and Test Conference (EDTC) February 1994 |
| H. Wittmann and M. Henftling Efficient Path Identification for Delay Testing --- Time and Space Optimization European Design and Test Conference (EDTC) February 1994 |
| B. Wurth and N. Wehn Efficient calculation of Boolean relations for multi-level logic optimization European Design and Test Conference (EDTC) February 1994 |
| K. Antreich and H. Graeb and C. Wieser Circuit analysis and optimization driven by worst-case distances IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems January 1994 |
| K. J. Antreich and H. Graeb and R. K. Koblitz Advanced Yield Optimization Techniques Elsevier Science Publishers, Amsterdam 1994 |
| H. Bauer Verteilte diskrete Simulation komplexer Systeme PhD Thesis 1994 |
| K. Doll Ein iteratives Verfahren zum Plazieren von Zellen bei der Layoutsynthese integrierter Schaltungen PhD Thesis 1994 |
| C. Sporrer Verfahren zur Schaltungspartitionierung für die parallele Logiksimulation PhD Thesis 1994 |
| U. Schlichtmann Logiksynthese für komplexe anwenderprogrammierbare elektronische Bausteine PhD Thesis 1994 |
| C. Wieser Schaltkreisanalyse mit Worst-Case Abständen PhD Thesis 1994 |
| K. J. Antreich and M. Hermann and F. Dresig Geteilte Logiksynthese für FPGAs designelektronik 1994 |
1993
| B. Wurth and N. Wehn Multi-Level Logic Optimization with Boolean Relations IFIP Workshop on Logic and Architecture Synthesis December 1993 |
| U. Schlichtmann Disjunkte Dekomposition Boolescher Funktionen: Eine Neue Betrachtungsweise Entwurf Integrierter Schaltungen (E.I.S.-Workshop) November 1993 |
| P. A. Krauss and K. J. Antreich Application of Fault Parallelism to the Automatic Test Pattern Generation for Sequential Circuits Lecture Notes in Computer Science No.~732: Parallel Computer Architectures: Theory, Hardware, Software, Applications August 1993 |
| U. Schlichtmann and F. Brglez Efficient Boolean Matching in Technology Mapping with Very Large Cell Libraries IEEE Custom Integrated Circuits Conference (CICC) May 1993 |
| U. Schlichtmann and F. Brglez and P. Schneider Efficient Boolean Matching Based on Unique Variable Ordering International Workshop on Logic Synthesis (IWLS) May 1993 |
| K. Fuchs and H. C. Wittmann and K. J. Antreich Fast Test Pattern Generation for all Path Delay Faults Considering Various Test Classes European Test Conference (ETC) April 1993 |
| K. Fuchs and H. C. Wittmann and K. Huber Zur Synthese dynamisch testbarer kombinatorischer Schaltungen ITG/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen March 1993 |
| H. C. Wittmann and B. H. Seiß and K. J. Antreich Using Circuit Hierarchy for Fault Simulation in Combinational and Sequential Circuits European Conference on Design Automation (EDAC) February 1993 |
| M. Hermann and U. Schlichtmann and K. J. Antreich Fast Technology Mapping for Multiplexor-based Architectures with Area/Delay Tradeoff European Conference on Design Automation (EDAC) February 1993 |
| H. Graeb Schaltkreisoptimierung mit Worst-Case-Abständen als Zielgrößen PhD Thesis 1993 |
| R. Hartmann Synthese von DSP-Algorithmen für flexible Multiprozessorstrukturen PhD Thesis 1993 |
| M. Utesch Zur graphenbasierten hierarchie-erhaltenden Adaptierung des Maskenlayouts integrierter Schaltungen PhD Thesis 1993 |
| K. Erhard Flächenminimierung von Stromversorgungsnetzen für hochintegrierte Schaltungen PhD Thesis 1993 |
| B. M. Rieß and K. Doll and F. M. Johannes Partitionierung hochkomplexer Schaltungen unter Nutzung von Plazierungsinformation 6. E.I.S.-Workshop 1993 |
| H. Graeb and C. Wieser and K. Antreich Improved methods for worst-case analysis and optimization incorporating operating tolerances ACM/IEEE Design Automation Conference (DAC) 1993 |
| C. Sporrer and H. Bauer Corolla Partitioning for Distributed Logic Simulation of VLSI-Circuits ACM/SCS/IEEE Workshop on Parallel and Distributed Simulation (PADS) 1993 |
| C. Wieser and H. Graeb Verbesserte Methoden zum Toleranzentwurf analoger integrierter Schaltungen GME/ITG-Diskussionssitzung Entwicklung von Analogschaltungen mit CAE-Methoden 1993 |
| H. Spruth and F. M. Johannes Architectures for Parallel Slicing Enumeration in VLSI Layout Lecture Notes in Computer Science No.~732: Parallel Computer Architectures: Theory, Hardware, Software, Applications 1993 |
| H. Bauer and C. Sporrer Reducing Rollback Overhead in Time-Warp Based Distributed Simulation with Optimized Incremental State Saving SCS/IEEE Annual Simulation Symposium (ASS) 1993 |
| C. Kredler and C. Zillober and F. M. Johannes and G. Sigl An application of preconditioned conjugate gradients to relative placement in chip design International Journal for Numerical Methods in Engineering 1993 |
| K. Antreich and H. Graeb and C. Wieser Practical methods for worst-case and yield analysis of analog integrated circuits International Journal of High Speed Electronics and Systems 1993 |
| H. Graeb and C. Wieser Methoden zum Toleranzentwurf, Teil 1 designelektronik 1993 |
1992
| F. Fink and K. Fuchs and M. H. Schulz Robust and Nonrobust Path Delay Fault Simulation by Parallel Processing of Patterns IEEE Transactions on Computers December 1992 |
| B. H. Seiß and H. C. Wittmann Highly Efficient Fault Simultation Exploiting Hierarchy in Circuit Description IEEE Asian Test Symposium (ATS) November 1992 |
| H. C. Wittmann and B. H. Seiß Hierarchische Fehlersimulation in kombinatorischen Schaltungen ITG/GME/GI--Fachtagung Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme November 1992 |
| M. Hermann and U. Schlichtmann Schnelle Logiksynthese für FPGAs mit Optimierung des Zeitverhaltens ITG/GME/GI-Fachtagung Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme November 1992 |
| H. Spruth and G. Sigl Parallel Algorithms for Slicing Based Final Placement European Design Automation Conference with EURO-VHDL (EURO-DAC) September 1992 |
| U. Schlichtmann and F. Brglez and M. Hermann Characterization of Boolean Functions for Rapid Matching in EPGA Technology Mapping ACM/IEEE Design Automation Conference (DAC) June 1992 |
| H. C. Wittmann Algorithmen zur schnellen Testmustergenerierung und Fehlersimulation für Verzögerungsfehler GMD/Ariadne-Workshop March 1992 |
| E. Auth and J. Kastner ESSENTIAL: Ein automatisches Testmustergenerierungsystem für synchrone Schaltwerke ITG/GI-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen March 1992 |
| D. Pellkofer Schnelle Fehlersimulation in digitalen Schaltungen PhD Thesis 1992 |
| G. Sigl Plazierung der Zellen bei der Layoutsynthese mittels Partitionierung und quadratischer Optimierung PhD Thesis 1992 |
| V. Eisele Zur Entwurfsoptimierung statischer Halbleiterspeicher PhD Thesis 1992 |
| S. Mayrhofer Ein laufzeitgesteuertes Plazierungsverfahren für den zellbasierten Layoutentwurf integrierter Schaltungen PhD Thesis 1992 |
| M. Rösch Schnelle Simulation des stationären Verhaltens nichtlinearer Schaltungen PhD Thesis 1992 |
| B. Seiß Testpunkteinbau und hierarchische Fehlersimulation in kombinatorischen Schaltungen PhD Thesis 1992 |
| G. Sigl Plazierung der Zellen bei der Layoutsynthese mittels Partitionierung und quadratischer Optimierung PhD Thesis 1992 |
| E. Auer Zur automatischen Layoutsynthese von Logikzellen PhD Thesis 1992 |
| E. Auth Automatische Testmustergenerierung in synchronen sequentiellen Schaltungen PhD Thesis 1992 |
| H. Bauer and C. Sporrer Distributed Logic Simulation and an Approach to Asynchronous GVT-Calculation ACM/SCS/IEEE Workshop on Parallel and Distributed Simulation (PADS) 1992 |
| H. Graeb and C. Wieser and K. Antreich Design verification considering manufacturing tolerances by using worst-case distances European Design Automation Conference with EURO-VHDL (EURO-DAC) 1992 |
| K. Erhard and F. M. Johannes and R. Dachauer Topology optimization techniques for power/ground networks in VLSI European Design Automation Conference with EURO-VHDL (EURO-DAC) 1992 |
| K. Doll and F. M. Johannes and G. Sigl Accurate Net Models for Placement Improvement by Network Flow Methods IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 1992 |
| V. Eisele and D. Schmitt-Landsiedel Makromodellierung des Lesevorgangs für die Architekturoptimierung schneller Halbleiterspeicher ITG-Fachtagung Mikroelektronik für die Informationstechnik 1992 |
| P. A. Krauss Fehlerparallelisierung bei der automatischen Testmustergenerierung für sequentielle Schaltungen ITG/GME/GI--Fachtagung Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme 1992 |
| H. Graeb and C. Wieser Erweiterte Schaltkreisanalyse mit Worst-Case-Abständen ITG/GME/GI-Fachtagung Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme 1992 |
| K. Doll and F. M. Johannes and G. Sigl Placement Improvement by Network Flow Methods Proceedings International Workshop on Layout Synthesis MCNC 1990 1992 |
| C. Sporrer and H. Bauer Partitioning VLSI-Circuits for Distributed Logic Simulation SCS European Simulation Multiconference (ESM) 1992 |
| M. Rösch and K. Antreich Fast steady-state simulation of nonlinear circuits in the frequency domain Archiv für Elektronik und Übertragungstechnik (AEÜ) 1992 |
| K. Erhard and F. M. Johannes Power/ground networks in VLSI: Are general graphs better than trees? INTEGRATION - the VLSI journal 1992 |
| H. Graeb and R. Lederle Circuit yield optimization by analyzing performance statistics Microprocessing and Microprogramming 1992 |
1991
| K. Fuchs and F. Fink and M. H. Schulz DYNAMITE: An Efficient Automatic Test Pattern Generation System for Path Delay Faults IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems October 1991 |
| H. Bauer and C. Sporrer and H. T. Krodel On Distributed Logic Simulation Using Time Warp IFIP International Conference on Very Large Scale Integration (VLSI) August 1991 |
| E. Auth and M. H. Schulz A Test--Pattern Generation Algorithm for Sequential Circuits IEEE Design and Test June 1991 |
| K. Doll and F. M. Johannes and G. Sigl Probabilistisches Plazieren von Standardzellen: Eine effiziente Alternative zu Simulated Annealing Entwurf Integrierter Schaltungen (E.I.S.-Workshop) April 1991 |
| F. Fink and K. Fuchs and M. H. Schulz An Efficient Parallel Pattern Gate Delay Fault Simulator with Accelerated Detected Fault Size Determination Capabilities European Test Conference (ETC) April 1991 |
| B. H. Seiß and P. M. Trouborst and M. H. Schulz Test Point Insertion for Scan--Based BIST European Test Conference (ETC) April 1991 |
| J. M. Kleinhans and G. Sigl and F. M. Johannes and K. J. Antreich GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems March 1991 |
| F. Fink Zur Simulation von Laufzeitfehlern in hochintegrierten Schaltungen PhD Thesis 1991 |
| K. Fuchs Testmustergenerierung zur Erkennung von Laufzeitfehlern in hochintegrierten Schaltungen PhD Thesis 1991 |
| H. Grabinski Theorie und Simulation von Leitbahnen Springer-Verlag 1991 |
| G. Sigl and K. Doll and F. M. Johannes Analytical Placement: A Linear or a Quadratic Objective Function? ACM/IEEE Design Automation Conference (DAC) 1991 |
| V. Eisele and D. Schmitt-Landsiedel Optimization and Architectural Evaluation of Regular Combinatoric Structures EUROMICRO Conference 1991 |
| G. Sigl and U. Schlichtmann Goal Oriented Slicing Enumeration through Shape Function Clipping European Conference on Design Automation (EDAC) 1991 |
| K. Antreich and H. Graeb Circuit optimization driven by worst-case distances IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 1991 |
| K. Doll and F. M. Johannes and G. Sigl DOMINO: Deterministic Placement Improvement with Hill-Climbing Capabilities IFIP International Conference on Very Large Scale Integration (VLSI) 1991 |
| K. Erhard and F. M. Johannes Area Minimization of IC power/ground nets by topology optimization IFIP International Conference on Very Large Scale Integration (VLSI) 1991 |
| K. Antreich and H. Graeb A unified approach towards nominal and tolerance design World Congress on Computation and Applied Mathematics (IMACS) 1991 |
| K. J. Antreich and K. Fuchs and F. Fink Testen von Laufzeitfehlern in digitalen Schaltungen Mikroelektronik me 1991 |
1990
| B. H. Seiß and M. H. Schulz Ein neues, effizientes Verfahren zum Testpunkteinbau in kombinatorischen Schaltungen Proceedings der GME/GI/ITG--Fachtagung October 1990 |
| K. J. Antreich and K. Fuchs and F. Fink Zum dynamischen Testen kombinatorischer Schaltungen Frequenz, Fachverlag Schiele & Schön April 1990 |
| K. M. Just and E. Auer and W. L. Schiele and A. Schwaferts Palace: A layout generator for SCVS logic blocks ACM/IEEE Design Automation Conference (DAC) 1990 |
| V. Eisele and B. Hoppe and O. Kiehl Transmission Gate Delay Models for Circuit Optimization European Conference on Design Automation (EDAC) 1990 |
| H. T. Krodel and K. J. Antreich An Accurate Model for Ambiguity Delay Simulation European Conference on Design Automation (EDAC) 1990 |
| K. J. Antreich and D. Pellkofer Fast Fault Simulation for VLSI--Logic (invited paper) XXIII General Assembly Of The International Union Of Radio Science (URSI) VLSI--CAD--Session 1990 |
| K. J. Antreich and H. T. Krodel Verfahren zur Logiksimulation und Laufzeitmodellierung in digitalen Schaltungen Archiv für Elektronik und Übertragungstechnik (AEÜ) 1990 |
| W. L. Schiele and A. Schwaferts and K. M. Just and E. Auer Ein Layoutgenerator für Logikblöcke in SCVS-Schaltungstechnik Archiv für Elektronik und Übertragungstechnik (AEÜ) 1990 |
| M. H. Schulz and H. Wunderlich Methoden der Testvorbereitung zum IC-Entwurf Mikroelektronik me 1990 |
| K. Antreich A case history of cooperation in design automation research Siemens Review R&D Special 1990 |
1989
| T. M. Sarfert and R. G. Markgraf and E. Trischler and M. H. Schulz Hierarchical Test Pattern Generation Based on High--Level Primitives IEEE International Test Conference (ITC) August 1989 |
| H. C. Ranke and F. M. Johannes Macrocell Placement by Global Optimization with Uniform Cell Distribution IFIP International Conference on Very Large Scale Integration (VLSI) August 1989 |
| M. H. Schulz and E. Auth Improved Deterministic Test Pattern Generation with Applications to Redundancy Identification IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems July 1989 |
| M. H. Schulz and F. Fink and K. Fuchs Parallel Pattern Fault Simulation of Path Delay Faults ACM/IEEE Design Automation Conference (DAC) June 1989 |
| M. H. Schulz and D. Pellkofer A Three--Valued Fast Fault Simulator for Scan--Based VLSI--Logic European Test Conference (ETC) April 1989 |
| M. H. Schulz and B. H. Seiß and F. Brglez Hierarchical Fault Simulation in Combinational Circuits European Test Conference (ETC) April 1989 |
| M. H. Schulz and E. Auth ESSENTIAL: An Efficient Self--Learning Test Pattern Generation Algorithm for Sequential Circuits 12th Annual IEEE Workshop on Design for Testability April 1989 |
| J. M. Kleinhans Ein Plazierungsverfahren für den zellenbasierten Layoutentwurf hochintegrierter Schaltungen PhD Thesis 1989 |
| H. T. Krodel Verfahren zur Logiksimulation komplexer digitaler Schaltungen mit flexibler Modellierung PhD Thesis 1989 |
| F. Pörnbacher Zur interaktiven Dimensionierung analoger integrierter Schaltungen unter Berücksichtigung von Nebenbedingungen PhD Thesis 1989 |
| B. Hoppe and O. Kiehl and T. Huber and D. Schmitt-Landsiedel and G. Neuendorf and V. Eisele Polynomial delay models for optimization - based transistor sizing in digital CMOS VLSI circuits European Conference on Circuit Theory and Design (ECCTD) 1989 |
| F. Pörnbacher A new method supporting the nominal design of analog integrated circuits with regard to constraints European Conference on Circuit Theory and Design (ECCTD) 1989 |
| J. M. Kleinhans and G. Sigl and F. M. Johannes Sea-of-Gates Placement by Simultaneous Quadratic Programming Combined with Improved Partitioning IFIP International Conference on Very Large Scale Integration (VLSI) 1989 |
| H. Wunderlich and M. H. Schulz Methoden der Testvorbereitung ITG-Fachtagung Mikroelektronik für die Informationstechnik 1989 |
| F. M. Johannes Layout-Entwurf Tagungsband ITG-Fachtagung für die Informationstechnik 1989 |
| K. Antreich and K. Zibert Entwurfstechnik für integrierte Schaltungen Mikroelektronik me 1989 |
| D. A. Mlynski and F. M. Johannes and U. P. Lauther and W. Schiele and C. Federschmidt and W. Fleig and H. Vollmer Physikalischer Entwurf von integrierten Schaltungen Mikroelektronik me 1989 |
| F. Pörnbacher CANDI: Ein Programmsystem zur Unterstützung des Entwurfs integrierter Schaltungen ntzArchiv 1989 |
1988
| J. M. Kleinhans and G. Sigl and F. M. Johannes GORDIAN: A New Global Optimization / Rectangle Dissection Method for Cell Placement IEEE/ACM International Conference on Computer-Aided Design (ICCAD) November 1988 |
| M. H. Schulz and E. Auth Advanced Automatic Test Pattern Generation and Redundancy Identification Techniques IEEE International Symposium on Fault-Tolerant Computing (FTCS) June 1988 |
| K. J. Antreich and J. M. Kleinhans and K. Fuchs Zwei- und dreilagiges Channel-Routing mit optimierter Zyklenbehandlung und Pfadverkürzung Archiv für Elektronik und Übertragungstechnik (AEÜ) January 1988 |
| M. H. Schulz and E. Trischler and T. M. Sarfert SOCRATES: A Highly Efficient Automatic Test Pattern Generation System IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems January 1988 |
| E. Trischler Zur Modellierung digitaler Schaltungen mit AND/OR--Graphen für die automatische Testmustergenerierung PhD Thesis 1988 |
| M. H. Schulz Testmustergenerierung und Fehlersimulation in digitalen Schaltungen mit hoher Komplexität PhD Thesis 1988 |
| A. Schütz Modulgeneratoren vereinfachen ASIC-Design Elektronik el 1988 |
| K. Antreich and P. Leibner and F. Pörnbacher Nominal design of integrated circuits on circuit level by an interactive improvement method IEEE Transactions on Circuits and Systems CAS 1988 |
| B. Schürmann Hierarchisches Top Down Chip Planning infospektrum 1988 |
1987
| M. H. Schulz and E. Trischler and T. M. Sarfert SOCRATES: A Highly Efficient Automatic Test Pattern Generation System IEEE International Test Conference (ITC) September 1987 |
| K. J. Antreich and M. H. Schulz Fast Fault Simulation for Scan--Based VLSI--Logic Proceedings of the European Conference on Circuit Theory and Design 1987 September 1987 |
| M. H. Schulz and F. Brglez Accelerated Transition Fault Simulation ACM/IEEE Design Automation Conference (DAC) June 1987 |
| G. Müller-Liebler Zur stochastischen Optimierung beim Entwurf integrierter Schaltungen PhD Thesis 1987 |
| K. M. Just Zur automatischen Plazierung der Module bei der Layout-Synthese PhD Thesis 1987 |
| J. M. Kleinhans Channel-Routing für zwei und drei Verdrahtungsebenen mit Behandlung zyklischer Konflikte Entwurf Integrierter Schaltungen (E.I.S.-Workshop) 1987 |
| J. M. Kleinhans Efficient algorithms for two- and three-layer channel routing IEEE Proceedings VLSI and Computers, International Conference on Computer Technology, Systems and 1987 |
| F. Pörnbacher Switch-Level-Simulation nach dem CSA-Verfahren ntzArchiv 1987 |
1986
| K. J. Antreich and M. H. Schulz Zur schnellen Fehlersimulation in kombinatorischen Schaltungen Archiv für Elektronik und Übertragungstechnik (AEÜ) June 1986 |
| K. M. Just Zur Plazierung von Standardzellen durch Lösen des Relativplazierungs- und Transportproblems Entwurf Integrierter Schaltungen (E.I.S.-Workshop) March 1986 |
| P. Leibner Ein interaktives Optimierungsverfahren zur rechnergestützten Dimensionierung integrierter Schaltungen PhD Thesis 1986 |
| K. M. Just and J. M. Kleinhans and F. M. Johannes On The Relative Placement And The Transportation Problem For Standard-Cell Layout ACM/IEEE Design Automation Conference (DAC) 1986 |
| P. Leibner Rechnerunterstützte Dimensionierung integrierter Schaltungen mittels eines interaktiven Optimierungsverfahrens Entwurf Integrierter Schaltungen (E.I.S.-Workshop) 1986 |
| P. Leibner On an Interactive Optimization Method for the Design of Integrated Circuits (in German) Archiv für Elektronik und Übertragungstechnik (AEÜ) 1986 |
1985
| K. M. Just and J. M. Kleinhans Zur simultanen Plazierung von Moduln integrierter Schaltungen Archiv für Elektronik und Übertragungstechnik (AEÜ) July 1985 |
| E. Trischler and M. H. Schulz Applications of Testability Analysis to ATG: Methods and Experimental Results IEEE International Symposium on Circuits and Systems (ISCAS) June 1985 |
1984
| F. Kirsch Rechnergestützte Lösungsverfahren zur Relativplazierung bei der Layoutsynthese PhD Thesis 1984 |
| K. Antreich and S. Huss An Interactive Optimization Technique for the Nominal Design of Integrated Circuits IEEE Transactions on Circuits and Systems CAS 1984 |
1983
| K. Antreich and J. Armaos A general approach to statistical circuit design European Conference on Circuit Theory and Design (ECCTD) 1983 |
| K. Antreich and P. Leibner Nominal Design of Integrated Circuits by Interactive Optimization IEEE International Symposium on Circuits and Systems (ISCAS) 1983 |
| F. M. Johannes and K. M. Just and K. J. Antreich On the Force Placement of Logic Arrays Proceedings European Conference on Circuit Theory and Design (ECCTD) 1983 |
1982
| K. J. Antreich and F. M. Johannes and F. H. Kirsch Zur Plazierung von Bauelementen Archiv für Elektronik und Übertragungstechnik (AEÜ) January 1982 |
| J. Armaos Zur Optimierung der Fertigungsausbeute elektrischer Schaltungen unter Berücksichtigung der Parametertoleranzen PhD Thesis 1982 |
| S. Huss Zur interaktiven Optimierung integrierter Schaltungen PhD Thesis 1982 |
| R. Koblitz Ein Verfahren zur Entwurfszentrierung elektrischer Schaltungen. PhD Thesis 1982 |
| K. J. Antreich and F. M. Johannes and F. H. Kirsch A New Approach for Solving the Placement Problem Using Force Models IEEE International Symposium on Circuits and Systems (ISCAS) 1982 |
| R. Koblitz Interactive Design Centering by an Efficient Assessment Criterion IEEE International Symposium on Circuits and Systems (ISCAS) 1982 |
| K. Antreich and S. Huss An Interactive Approach to the Optimization of Integrated Circuits (in German) Archiv für Elektronik und Übertragungstechnik (AEÜ) 1982 |
| F. H. Kirsch Ein Lösungsverfahren zur Plazierung von Bauelementen mittels eines Kräftemodells Archiv für Elektronik und Übertragungstechnik (AEÜ) 1982 |
| K. Antreich and R. Koblitz Design Centering by Yield Prediction IEEE Transactions on Circuits and Systems CAS 1982 |
1981
| W. Hauck Zum rechnergestützten Entwurf quasilinearer Systeme PhD Thesis 1981 |
| K. Antreich and R. Koblitz An interactive procedure to design centering IEEE International Symposium on Circuits and Systems (ISCAS) 1981 |
| J. Armaos A general statistical approach to design centering and tolerancing (in German) Archiv für Elektronik und Übertragungstechnik (AEÜ) 1981 |
1980
| K. Antreich and R. Koblitz A new approach to design centering based on a multiparameter yield-prediction formula IEEE International Symposium on Circuits and Systems (ISCAS) 1980 |
| K. Antreich and G. Müller On the Interactive Optimization of Electrical Networks (in German) Archiv für Elektronik und Übertragungstechnik (AEÜ) 1980 |
| R. Koblitz Design centering and tolerance assignment of electrical circuits with Gaussian-distributed parameter values (in German) Archiv für Elektronik und Übertragungstechnik (AEÜ) 1980 |
1979
| G. Müller Interaktive Schaltungsoptimierung und rechnergestützter Abgleich PhD Thesis 1979 |
1978
| K. Antreich and R. Koblitz Zur Vereinheitlichung der Toleranz- und Empfindlichkeitsanalyse elektrischer Netzwerke Archiv für Elektronik und Übertragungstechnik (AEÜ) 1978 |
1976
| G. Müller On Computer-Aided Tuning of Microwave Filters IEEE International Symposium on Circuits and Systems (ISCAS) 1976 |
