Electronic System Level (ESL)
Virtual Prototyping and Virtual Platforms
In the context of our work VPs are detailed enough to emulate the embedded target software. They can work as platforms for architecture exploration, early software development and system-level verification.
VPs ascend to higher abstraction level than the conventional Register Transfer Level (RTL) for higher simulation performance. Transaction Level Modeling (TLM) using SystemC is a very, if not the most, widely adopted methodology for this purpose. In TLM, communication between modules is abstracted as transaction. Transactions are evoked by (non-clocked) events and realized by function calls.
Current research focus:
- Fast CPU models: For TLM simulation of SoCs, the emulation of the target SW code can quickly become the performance bottleneck. TUM EDA researches CPU models that can simulate target code siginficantly faster than conventional CPU models. For this we investigate so called host-compiled SW simulation, which compiles the SW directly for the simulation host. Here we developed an annotation tool to recover the timing information of the target SW for ultra-fast but timing-accurate simulation.
- Early Functional Safety Evaluation by VP-level Error Injection: In safety-critical applications such as human-robot interaction or assisted and autonomous driving, the system must preserve a safe state even in the presence of HW faults. HW faults in the embedded electronics may be caused by particle strikes onto the integrated curcuits (ICs) due to radiation, IC aging or supply voltage drops. In order to develop future complex systems for safety critical applications, we investigate methods for early evaluation of the safety concepts. We use VPs and VP-level fault injection with focus on CPUs and Firmware safety mechanisms.
Model-based Design Methods for SoCs and NoCs
Model-based design methods and code generation can boost design productivity for developing tomorrow's Systems-on-Chip (SoCs) and Networks-onChip(NoCs). We develop software tools based on the Eclipse EMF environment to enable model-driven design methods for SoCs and NoCs.
Our current research directions are:
- Graph-rewriting based IP Integration (GRIP): Graph rewriting is a efficient and proven method for structural explorations. We use graph rewriting in our GRIP approach to automatically integrate acceleration IP blocks into FPGA-based SoCs into FPGA-based SoC chipsets such as the Xilinx Zynq chip. The IP blocks are organized with so-called GRIP integration rules in a library. By using model-based approaches based on the industrial IP-Xact meta-model we are able to automatically integrate HW accelerators for video processing, and generate the SW driver code for Linux or bare-metal integration. The user can use the IP library with the same ease as a SW library, such that we refer to this as a HW-accelerated SW library. Additionally graph rewriting can explore different SoC architectures to avoid communication bottlenecks and make best use of FPGA resources.
- Application-specific NoC Synthesis: Rising complexity of modern SoCs leads to increasing communication between the cores. Networks-on-chip (NoCs) have been proposed as new communication architecture because they are expected to scale better with the increasing communication demands. If the application is known at design time, custom SoC chips also require a custom appplication-specific NoC structure. In this project, methods are investigated that find NoC stuctures, which feature an optimal compromise between area, power and latencies.