Digital System Design with VHDL and System C
|Language of instruction||German|
|Position within curricula||See TUMonline|
- 13.03.2020 15:00-18:00 2999, Seminarraum
- 16.03.2020 09:00-20:30 2999, Seminarraum
- 17.03.2020 09:00-20:30 2999, Seminarraum
- 18.03.2020 09:00-20:30 2999, Seminarraum
- 19.03.2020 09:00-20:30 2999, Seminarraum
- 20.03.2020 09:00-20:30 2999, Seminarraum
- 23.03.2020 09:00-12:00 2999, Seminarraum
- 24.03.2020 10:00-11:15 2999, Seminarraum
Course criteria & registration
See TUMonlineNote: Registration on TUMOnline before the first lecture
The students will learn the abstraction, modeling and design techniques. Furthermore, the students will be familiar with an industrial design system and the modeling language VHDL (WS) and System C (SS).
ATTENTION: IN WS 2019/20 THIS IS A BLOCK COURSE OUTSIDE THE REGULAR COURSE PERIOD IN THE LECTURE-FREE TIME AFTER WS 2019/20. DATES: LECTURE Mon-Fri 4-8 March 2019 8:00-12:00 und 13:00-18:00, room 2999 (2977 for lab exercises) EXAM Mon 11 March 2019 16:00, room 2999 ATTENTION 2: In SS 2020 the course will NOT take place as well. Hardware description language VHDL and SystemC, design methodology with VHDL and SystemC, VHDL/SystemC modeling, VHDL/SystemC simulation and VHDL/SystemC synthesis, methods of logic synthesis, register-transfer synthesis and high-level synthesis; computer lab exercises in VHDL/SystemC modeling, automatic synthesis and selected synthesis methods.
Basic knowledge in digital design; one programming language (at best C or C++) is absolutely necessary.
Teaching and learning methods
As teaching method learning using examples will be used. According to one example (a MIPS2 subsystem) the requirements are motivated, presented and then generalized. The learning content will be deepened by team wok and incorporation of industrial working styles.
Examination with following parts: - Written examination at the end of the course (60 min., no notes allowed) (50%) - Graded homework/projects (4 parts: memory model, functional CPU model, behavioral CPU model, RTL CPU model) (50%)
Following materials are recommended: * Computer Organization And Design The Hardware/Software Interface; David A. Patterson, John L. Hennessy, Elsevier * John L. Hennessy, David A. Patterson: Computer Architecture - A Quantitative Approach, Elsevier / Morgan Kaufmanns Publishers. * Dominic Sweetman: See MIPS Run Linux, Elsevier / Morgan Kaufmanns Publishers. * Peter Ashenden: The Designer’s Guide to VHDL, Morgan Kaufmann Series in Systems on Silicon) * Thinking in C++ 2nd Edition by Bruce Eckel * SystemC: From the Ground Up (the Kluwer International Series in Engineering & Computer Science) (Hardcover) * Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems. Internet Resources: * http://en.wikipedia.org/wiki/MIPS_architecture * http://www.mips.com/products/processors/ * http://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf